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IS61LPS51218A-200B2 PDF预览

IS61LPS51218A-200B2

更新时间： 2024-11-21 04:58:35
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路静态存储器
页数 文件大小 规格书
32页 209K
描述
256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

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IS61LPS51218A-200B2 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：BGA
包装说明：BGA, BGA119,7X17,50针数：119
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.49
最长访问时间：3.1 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：200 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B119JESD-609代码：e0
长度：22 mm内存密度：9437184 bit
内存集成电路类型：CACHE SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：119字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：512KX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA119,7X17,50封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：2.41 mm
最大待机电流：0.1 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.25 mA
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

IS61LPS51218A-200B2 数据手册

 浏览型号IS61LPS51218A-200B2的Datasheet PDF文件第2页浏览型号IS61LPS51218A-200B2的Datasheet PDF文件第3页浏览型号IS61LPS51218A-200B2的Datasheet PDF文件第4页浏览型号IS61LPS51218A-200B2的Datasheet PDF文件第5页浏览型号IS61LPS51218A-200B2的Datasheet PDF文件第6页浏览型号IS61LPS51218A-200B2的Datasheet PDF文件第7页 
®
IS61VPS25636A IS61LPS25636A  
IS61VPS51218A IS61LPS51218A  
ISSI  
256K x 36, 512K x 18  
MAY 2005  
9 Mb SYNCHRONOUS PIPELINED,  
SINGLE CYCLE DESELECT STATIC RAM  
DESCRIPTION  
FEATURES  
The ISSI IS61LPS/VPS25636A and IS61LPS/  
VPS51218Aarehigh-speed,low-powersynchronousstatic  
RAMsdesignedtoprovideburstable,high-performancememory  
for communication and networking applications. The  
IS61LPS/VPS25636A is organized as 262,144 words by  
36 bits and the IS61LPS/VPS51218A is organized as  
524,288 words by 18 bits. Fabricated with ISSI's ad-  
vanced CMOS technology, the device integrates a 2-bit  
burst counter, high-speed SRAM core, and high-drive  
capability outputs into a single monolithic circuit. All  
synchronous inputs pass through registers controlled by  
a positive-edge-triggered single clock input.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Burst sequence control using MODE input  
• Three chip enable option for simple depth  
expansion and address pipelining  
• Common data inputs and data outputs  
• Auto Power-down during deselect  
• Single cycle deselect  
Write cycles are internally self-timed and are initiated by  
therisingedgeoftheclockinput. Writecyclescanbeone  
tofourbyteswideascontrolledbythewritecontrolinputs.  
• Snooze MODE for reduced-power standby  
• JTAG Boundary Scan for PBGA package  
• Power Supply  
Separatebyteenablesallowindividualbytestobewritten.  
The byte write operation is performed by using the byte  
write enable (BWE) input combined with one or more  
individual byte write signals (BWx). In addition, Global  
Write (GW) is available for writing all bytes at one time,  
regardless of the byte write controls.  
LPS: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%  
VPS: VDD 2.5V + 5%, VDDQ 2.5V + 5%  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
inputpins.Subsequentburstaddressescanbegenerated  
internally and controlled by the ADV (burst address  
advance) input pin.  
• JEDEC 100-Pin TQFP, 119-ball PBGA, and  
165-ball PBGA packages  
• Lead-free available  
The mode pin is used to select the burst sequence order,  
Linear burst is achieved when this pin is tied LOW.  
Interleave burst is achieved when this pin is tied HIGH or  
left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
250  
2.6  
4
200  
3.1  
5
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
ns  
Frequency  
250  
200  
MHz  
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability  
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany  
publishedinformationandbeforeplacingordersforproducts.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
1
04/29/05  
1234567...32

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与IS61LPS51218A-200B2相关器件

型号 品牌 获取价格 描述 数据表
IS61LPS51218A-200B2I ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS51218A-200B3 ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS51218A-200B3I ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS51218A-200TQ ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS51218A-200TQ2I ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS51218A-200TQ2LI ISSI

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 		Cache SRAM, 512KX18, 3.1ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, LQFP-100
IS61LPS51218A-200TQI ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS51218A-200TQI-TR ISSI

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 		IC SRAM 9M PARALLEL 100TQFP
IS61LPS51218A-200TQLI ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS51218A-200TQLI-TR ISSI

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 		IC SRAM 9M PARALLEL 100TQFP

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