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IS61LPS25672A-250B1I PDF预览

IS61LPS25672A-250B1I

更新时间： 2024-11-21 04:58:35
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路静态存储器
页数 文件大小 规格书
34页 220K
描述
256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

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IS61LPS25672A-250B1I 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：BGA
包装说明：BGA, BGA209,11X19,40针数：209
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.52
Is Samacsys：N最长访问时间：2.6 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：250 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B209
JESD-609代码：e0长度：22 mm
内存密度：18874368 bit内存集成电路类型：CACHE SRAM
内存宽度：72功能数量：1
端子数量：209字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：256KX72输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA209,11X19,40封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：1.95 mm
最大待机电流：0.125 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.65 mA
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

IS61LPS25672A-250B1I 数据手册

 浏览型号IS61LPS25672A-250B1I的Datasheet PDF文件第2页浏览型号IS61LPS25672A-250B1I的Datasheet PDF文件第3页浏览型号IS61LPS25672A-250B1I的Datasheet PDF文件第4页浏览型号IS61LPS25672A-250B1I的Datasheet PDF文件第5页浏览型号IS61LPS25672A-250B1I的Datasheet PDF文件第6页浏览型号IS61LPS25672A-250B1I的Datasheet PDF文件第7页 
IS61VPS25672A IS61LPS25672A  
IS61VPS51236A IS61LPS51236A  
IS61VPS102418A IS61LPS102418A  
®
ISSI  
256K x 72, 512K x 36, 1024K x 18  
18Mb SYNCHRONOUS PIPELINED,  
SINGLE CYCLE DESELECT STATIC RAM  
FEBRUARY 2005  
DESCRIPTION  
FEATURES  
The ISSIIS61LPS/VPS51236A,IS61LPS/VPS102418A,  
andIS61LPS/VPS25672Aarehigh-speed,low-powersyn-  
chronous staticRAMs designedtoprovideburstable, high-  
performance memory for communication and networking  
applications. The IS61LPS/VPS51236A is organized as  
524,288 words by 36 bits, the IS61LPS/VPS102418A is  
organizedas1,048,576wordsby18bits,andtheIS61LPS/  
VPS25672A is organized as 262,144 words by 72 bits.  
Fabricated with ISSI's advanced CMOS technology, the  
deviceintegratesa2-bitburstcounter,high-speedSRAM  
core,andhigh-drivecapabilityoutputsintoasinglemono-  
lithic circuit. All synchronous inputs pass through regis-  
ters controlled by a positive-edge-triggered single clock  
input.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Burst sequence control using MODE input  
• Three chip enable option for simple depth  
expansion and address pipelining  
• Common data inputs and data outputs  
• Auto Power-down during deselect  
• Single cycle deselect  
Write cycles are internally self-timed and are initiated by  
therisingedgeoftheclockinput. Writecyclescanbeone  
tofourbyteswideascontrolledbythewritecontrolinputs.  
• Snooze MODE for reduced-power standby  
• JTAG Boundary Scan for PBGA package  
• Power Supply  
Separatebyteenablesallowindividualbytestobewritten.  
The byte write operation is performed by using the byte  
write enable (BWE) input combined with one or more  
individual byte write signals (BWx). In addition, Global  
Write (GW) is available for writing all bytes at one time,  
regardless of the byte write controls.  
LPS: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%  
VPS: VDD 2.5V + 5%, VDDQ 2.5V + 5%  
• JEDEC 100-Pin TQFP, 119-ball PBGA, 165-ball  
PBGA, and 209-ball (x72) packages  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
inputpins.Subsequentburstaddressescanbegenerated  
internally and controlled by the ADV (burst address  
advance) input pin.  
• Lead-free available  
The mode pin is used to select the burst sequence order,  
Linear burst is achieved when this pin is tied LOW.  
Interleave burst is achieved when this pin is tied HIGH or  
left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
250  
2.6  
4
200  
3.1  
5
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
ns  
Frequency  
250  
200  
MHz  
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability  
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany  
publishedinformationandbeforeplacingordersforproducts.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. D  
1
02/11/05  
1234567...34

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与IS61LPS25672A-250B1I相关器件

型号 品牌 获取价格 描述 数据表
IS61LPS25672A-250B1L ISSI

获取价格

 		256Kx72,512Kx36,1024Kx18 18Mb SYNCHRONOUS PIPELINED,SINGLE CYCLE DESELECT STATIC RAM
IS61LPS409618B-200TQL ISSI

获取价格

 		Cache SRAM, 4MX18, 3.1ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-100
IS61LPS409618B-200TQLI ISSI

获取价格

 		Cache SRAM, 4MX18, 3.1ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, LQFP-100
IS61LPS409618B-200TQLI-TR ISSI

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 		IC SRAM 72MBIT 200MHZ 100TQFP
IS61LPS51218A ISSI

获取价格

 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS51218A_12 ISSI

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 		256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC R
IS61LPS51218A-200B2 ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS51218A-200B2I ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS51218A-200B3 ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS51218A-200B3I ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

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