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IS61LPS25636J-166BI PDF预览

IS61LPS25636J-166BI

更新时间： 2024-09-17 14:42:55
品牌 Logo 应用领域
美国芯成 - ISSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
29页 177K
描述
Cache SRAM, 256KX36, 3.5ns, CMOS, PBGA119, PLASTIC, BGA-119

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IS61LPS25636J-166BI 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：PLASTIC, BGA-119针数：119
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.46
Is Samacsys：N最长访问时间：3.5 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：166 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B119
JESD-609代码：e0长度：22 mm
内存密度：9437184 bit内存集成电路类型：CACHE SRAM
内存宽度：36功能数量：1
端子数量：119字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：256KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA119,7X17,50封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：240电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：2.41 mm
最大待机电流：0.04 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.135 mA
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：14 mm
Base Number Matches：1

IS61LPS25636J-166BI 数据手册

 浏览型号IS61LPS25636J-166BI的Datasheet PDF文件第2页浏览型号IS61LPS25636J-166BI的Datasheet PDF文件第3页浏览型号IS61LPS25636J-166BI的Datasheet PDF文件第4页浏览型号IS61LPS25636J-166BI的Datasheet PDF文件第5页浏览型号IS61LPS25636J-166BI的Datasheet PDF文件第6页浏览型号IS61LPS25636J-166BI的Datasheet PDF文件第7页 
IS61LPS25632T/D/J  
IS61LPS25636T/D/J  
IS61LPS51218T/DJ  
®
ISSI  
256K x 32, 256K x 36, 512K x 18  
SYNCHRONOUS PIPELINED,  
PRELIMINARY INFORMATION  
FEBRUARY 2002  
SINGLE-CYCLE DESELECT STATIC RAM  
DESCRIPTION  
FEATURES  
The ISSI IS61LPS25632T/D/J,IS61LPS25636T/D/J,and  
IS61LPS51218T/D/JT/D/JT/D/Jarehigh-speed,low-power  
synchronousstaticRAMsdesignedtoprovideburstable,high-  
performancememoryforcommunicationandnetworkingappli-  
cations.TheIS61LPS25632T/D/Jisorganizedas262,144  
wordsby32bitsandtheIS61LPS25636T/D/Jisorganized  
as262,144wordsby36bits.TheIS61LPS51218T/D/JT/D/  
JT/D/Jisorganizedas524,288wordsby18bits.Fabricated  
with ISSI's advanced CMOS technology, the device inte-  
grates a 2-bit burst counter, high-speed SRAM core, and  
high-drivecapabilityoutputsintoasinglemonolithiccircuit.  
Allsynchronousinputspassthroughregisterscontrolledby  
a positive-edge-triggered single clock input.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Linear burst sequence control using MODE  
input  
•
Three chip enable option for simple depth  
expansion and address pipelining  
• Common data inputs and data outputs  
• JEDEC 100-Pin TQFP and  
119-pin PBGA package  
Writecyclesareinternallyself-timedandareinitiatedbythe  
risingedgeoftheclockinput.Writecyclescanbeonetofour  
bytes wide as controlled by the write control inputs.  
• Power Supply  
+3.3V Vcc  
Separate byte enables allow individual bytes to be written.  
Bytewriteoperationisperformedbyusingbytewriteenable  
(BWE).inputcombinedwithoneormoreindividualbytewrite  
signals(BWx).Inaddition,GlobalWrite(GW)isavailablefor  
writing all bytes at one time, regardless of the byte write  
controls.  
+3.3V or 2.5 VccQ (I/O)  
• Auto Power-down during deselect  
• Single cycle deselect  
• Snooze MODE for reduced-power standby  
• JTAG Boundary Scan for PBGA package  
• T Versions (three chips selects)  
• D Versions (two chips selects)  
• J Version (PBGA Pacakge with JTAG)  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
input pins. Subsequent burst addresses can be generated  
internally and controlled by the ADV (burst address ad-  
vance) input pin.  
The mode pin is used to select the burst sequence order,  
Linear burst is achieved when this pin is tied LOW. Inter-  
leave burst is achieved when this pin is tied HIGH or left  
floating.  
FAST ACCESS TIME  
Symbol  
Parameter  
Clock Access Time  
Cycle Time  
-250  
2.6  
4
-225  
2.8  
-200  
3.1  
5
-166  
3.5  
6
Units  
ns  
tKQ  
tKC  
4.4  
ns  
Frequency  
250  
225  
200  
166  
MHz  
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best  
possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
PRELIMINARYINFORMATION Rev. 00A  
1
02/10/02  
1234567...29

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与IS61LPS25636J-166BI相关器件

型号 品牌 获取价格 描述 数据表
IS61LPS25636J-200B ISSI

获取价格

 		Cache SRAM, 256KX36, 3.1ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61LPS25636J-225B ISSI

获取价格

 		Cache SRAM, 256KX36, 2.8ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61LPS25636T-225TQI ISSI

获取价格

 		Cache SRAM, 256KX36, 2.8ns, CMOS, PQFP100, TQFP-100
IS61LPS25636T-250TQ ISSI

获取价格

 		Cache SRAM, 256KX36, 2.6ns, CMOS, PQFP100, TQFP-100
IS61LPS25636T-5TQ ISSI

获取价格

 		Cache SRAM, 256KX36, 5ns, CMOS, PQFP100, TQFP-100
IS61LPS25672A ISSI

获取价格

 		256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC
IS61LPS25672A-250B1 ISSI

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 		256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC
IS61LPS25672A-250B1I ISSI

获取价格

 		256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC
IS61LPS25672A-250B1L ISSI

获取价格

 		256Kx72,512Kx36,1024Kx18 18Mb SYNCHRONOUS PIPELINED,SINGLE CYCLE DESELECT STATIC RAM
IS61LPS409618B-200TQL ISSI

获取价格

 		Cache SRAM, 4MX18, 3.1ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-100

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