Datasheet > IS61LPS25636T-225TQI

IS61LPS25636T-225TQI

更新时间： 2024-11-22 04:29:31

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
29页	174K
描述
Cache SRAM, 256KX36, 2.8ns, CMOS, PQFP100, TQFP-100

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IS61LPS25632T/D/J

IS61LPS25636T/D/J

IS61LPS51218T/DJ

ISSI

256K x 32, 256K x 36, 512K x 18

SYNCHRONOUS PIPELINED,

APRIL 2003

SINGLE-CYCLE DESELECT STATIC RAM

DESCRIPTION

FEATURES

The ISSI IS61LPS25632T/D/J,IS61LPS25636T/D/J,and

IS61LPS51218T/D/J are high-speed, low-power synchro-

nous static RAMs designed to provide burstable, high-

performance memory for communication and networking

applications. The IS61LPS25632T/D/J is organized as

262,144 words by 32 bits and the IS61LPS25636T/D/J is

organizedas262,144wordsby36bits.TheIS61LPS51218T/

D/J is organized as 524,288 words by 18 bits. Fabricated

with ISSI's advanced CMOS technology, the device inte-

grates a 2-bit burst counter, high-speed SRAM core, and

high-drivecapabilityoutputsintoasinglemonolithiccircuit.

Allsynchronousinputspassthroughregisterscontrolledby

a positive-edge-triggered single clock input.

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Linear burst sequence control using MODE

input

•

Three chip enable option for simple depth

expansion and address pipelining

• Common data inputs and data outputs

• JEDEC 100-Pin TQFP and

119-pin PBGA package

Writecyclesareinternallyself-timedandareinitiatedbythe

risingedgeoftheclockinput.Writecyclescanbeonetofour

bytes wide as controlled by the write control inputs.

• Power Supply

+3.3V V^DD

Separate byte enables allow individual bytes to be written.

Bytewriteoperationisperformedbyusingbytewriteenable

(BWE). Input combined with one or more individual byte

write signals (BWx). In addition, Global Write (GW) is

available for writing all bytes at one time, regardless of the

byte write controls.

+3.3V or 2.5 VDDQ (I/O)

• Auto Power-down during deselect

• Single cycle deselect

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for PBGA package

• T Version (three chips selects)

• D Version (two chips selects)

• J Version (PBGA Package with JTAG)

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally and controlled by the ADV (burst address ad-

vance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW. Inter-

leave burst is achieved when this pin is tied HIGH or left

floating.

FAST ACCESS TIME

Symbol

tKQ

Parameter

-250

2.6

-225

2.8

-200

3.1

-166

3.5

Units

Clock Access Time

Cycle Time

tKC

4.4

Frequency

250

225

200

166

MHz

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. A

04/01/03

12 3 4 5 6 7...29

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与IS61LPS25636T-225TQI相关器件

型号	品牌	获取价格	描述	数据表
IS61LPS25636T-250TQ	ISSI	获取价格	Cache SRAM, 256KX36, 2.6ns, CMOS, PQFP100, TQFP-100
IS61LPS25636T-5TQ	ISSI	获取价格	Cache SRAM, 256KX36, 5ns, CMOS, PQFP100, TQFP-100
IS61LPS25672A	ISSI	获取价格	256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC
IS61LPS25672A-250B1	ISSI	获取价格	256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC
IS61LPS25672A-250B1I	ISSI	获取价格	256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC
IS61LPS25672A-250B1L	ISSI	获取价格	256Kx72,512Kx36,1024Kx18 18Mb SYNCHRONOUS PIPELINED,SINGLE CYCLE DESELECT STATIC RAM
IS61LPS409618B-200TQL	ISSI	获取价格	Cache SRAM, 4MX18, 3.1ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-100
IS61LPS409618B-200TQLI	ISSI	获取价格	Cache SRAM, 4MX18, 3.1ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, LQFP-100
IS61LPS409618B-200TQLI-TR	ISSI	获取价格	IC SRAM 72MBIT 200MHZ 100TQFP
IS61LPS51218A	ISSI	获取价格	256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

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