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IS61LPS25636T-5TQ

更新时间： 2024-11-22 05:54:43
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器
页数 文件大小 规格书
22页 152K
描述
Cache SRAM, 256KX36, 5ns, CMOS, PQFP100, TQFP-100

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IS61LPS25636T-5TQ 数据手册

 浏览型号IS61LPS25636T-5TQ的Datasheet PDF文件第2页浏览型号IS61LPS25636T-5TQ的Datasheet PDF文件第3页浏览型号IS61LPS25636T-5TQ的Datasheet PDF文件第4页浏览型号IS61LPS25636T-5TQ的Datasheet PDF文件第5页浏览型号IS61LPS25636T-5TQ的Datasheet PDF文件第6页浏览型号IS61LPS25636T-5TQ的Datasheet PDF文件第7页 
IS61SPS25632T/D IS61LPS25632T/D  
IS61SPS25636T/D IS61LPS25636T/D  
®
IS61SPS51218T/D IS61LPS51218T/D ISSI  
256K x 32, 256K x 36, 512K x 18  
SYNCHRONOUS PIPELINE,  
SINGLE-CYCLE DESELECT STATIC RAM  
PRELIMINARYINFORMATION  
SEPTEMBER 2000  
FEATURES  
DESCRIPTION  
The ISSI IS61SPS25632,IS61SPS25636,IS61SPS51218,  
IS61LPS25632, IS61LPS25636, and IS61LPS51218 are  
high-speed, low-powersynchronousstaticRAMsdesigned  
toprovideaburstable, high-performance, secondarycachefor  
thePentium™,680X0™,andPowerPC™microprocessors.  
The IS61SPS25632 and IS61LPS25632 are organized as  
262,144 words by 32 bits and the IS61SPS25636 and  
IS61LPS25636 are organized as 262,144 words by 36 bits.  
The IS61SPS51218 and IS61LPS51218 are organized as  
524,288 words by 18 bits. Fabricated with ISSI's advanced  
CMOS technology, the device integrates a 2-bit burst  
counter, high-speed SRAM core, and high-drive capability  
outputs into a single monolithic circuit. All synchronous inputs  
passthroughregisterscontrolledbyapositive-edge-triggered  
single clock input.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Pentium™ or linear burst sequence control using  
MODE input  
•
Threechipenableoptionforsimpledepthexpansion  
and address pipelining  
• Common data inputs and data outputs  
• JEDEC 100-Pin TQFP and  
119-pin PBGA package  
• Single +3.3V, +10%, –5% power supply  
• Power-down snooze mode  
• 3.3V I/O For SPS  
Write cycles are internally self-timed and are initiated by the  
rising edge of the clock input. Write cycles can be from one  
to four bytes wide as controlled by the write control inputs.  
Separate byte enables allow individual bytes to be written.  
Byte write operation is performed by using byte write  
enable (BWE).input combined with one or more individual  
byte write signals (BWx). In addition, Global Write (GW)  
is available for writing all bytes at one time, regardless of  
the byte write controls.  
• 2.5V I/O For LPS  
• Single cycle deselect  
• Snooze MODE for reduced-power standby  
• T version (three chip selects)  
• D version (two chip selects)  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
input pins. Subsequent burst addresses can be generated  
internally and controlled by the ADV (burst address  
advance) input pin.  
The mode pin is used to select the burst sequence order,  
LinearburstisachievedwhenthispinistiedLOW. Interleave  
burst is achieved when this pin is tied HIGH or left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
-166*  
3.5  
6
-150  
3.8  
-133  
4
-5  
5
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
6.7  
7.5  
133  
10  
100  
ns  
Frequency  
166  
150  
MHz  
*This speed available only in SPS version  
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the  
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
PRELIMINARY INFORMATION Rev. 00A  
1
04/17/01  
1234567...22

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与IS61LPS25636T-5TQ相关器件

型号 品牌 获取价格 描述 数据表
IS61LPS25672A ISSI

获取价格

 		256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC
IS61LPS25672A-250B1 ISSI

获取价格

 		256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC
IS61LPS25672A-250B1I ISSI

获取价格

 		256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC
IS61LPS25672A-250B1L ISSI

获取价格

 		256Kx72,512Kx36,1024Kx18 18Mb SYNCHRONOUS PIPELINED,SINGLE CYCLE DESELECT STATIC RAM
IS61LPS409618B-200TQL ISSI

获取价格

 		Cache SRAM, 4MX18, 3.1ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-100
IS61LPS409618B-200TQLI ISSI

获取价格

 		Cache SRAM, 4MX18, 3.1ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, LQFP-100
IS61LPS409618B-200TQLI-TR ISSI

获取价格

 		IC SRAM 72MBIT 200MHZ 100TQFP
IS61LPS51218A ISSI

获取价格

 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS51218A_12 ISSI

获取价格

 		256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC R
IS61LPS51218A-200B2 ISSI

获取价格

 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

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