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IS61LPS25636D-5TQ PDF预览

IS61LPS25636D-5TQ

更新时间： 2024-09-17 14:42:55
品牌 Logo 应用领域
美国芯成 - ISSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
22页 152K
描述
Cache SRAM, 256KX36, 5ns, CMOS, PQFP100, TQFP-100

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IS61LPS25636D-5TQ 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：TQFP-100针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.48
最长访问时间：5 ns最大时钟频率 (fCLK)：100 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：9437184 bit内存集成电路类型：CACHE SRAM
内存宽度：36功能数量：1
端子数量：100字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：256KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：240电源：2.5,3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.3 mA最大供电电压 (Vsup)：3.63 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

IS61LPS25636D-5TQ 数据手册

 浏览型号IS61LPS25636D-5TQ的Datasheet PDF文件第2页浏览型号IS61LPS25636D-5TQ的Datasheet PDF文件第3页浏览型号IS61LPS25636D-5TQ的Datasheet PDF文件第4页浏览型号IS61LPS25636D-5TQ的Datasheet PDF文件第5页浏览型号IS61LPS25636D-5TQ的Datasheet PDF文件第6页浏览型号IS61LPS25636D-5TQ的Datasheet PDF文件第7页 
IS61SPS25632T/D IS61LPS25632T/D  
IS61SPS25636T/D IS61LPS25636T/D  
®
IS61SPS51218T/D IS61LPS51218T/D ISSI  
256K x 32, 256K x 36, 512K x 18  
SYNCHRONOUS PIPELINE,  
SINGLE-CYCLE DESELECT STATIC RAM  
PRELIMINARYINFORMATION  
SEPTEMBER 2000  
FEATURES  
DESCRIPTION  
The ISSI IS61SPS25632,IS61SPS25636,IS61SPS51218,  
IS61LPS25632, IS61LPS25636, and IS61LPS51218 are  
high-speed, low-powersynchronousstaticRAMsdesigned  
toprovideaburstable, high-performance, secondarycachefor  
thePentium™,680X0™,andPowerPC™microprocessors.  
The IS61SPS25632 and IS61LPS25632 are organized as  
262,144 words by 32 bits and the IS61SPS25636 and  
IS61LPS25636 are organized as 262,144 words by 36 bits.  
The IS61SPS51218 and IS61LPS51218 are organized as  
524,288 words by 18 bits. Fabricated with ISSI's advanced  
CMOS technology, the device integrates a 2-bit burst  
counter, high-speed SRAM core, and high-drive capability  
outputs into a single monolithic circuit. All synchronous inputs  
passthroughregisterscontrolledbyapositive-edge-triggered  
single clock input.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Pentium™ or linear burst sequence control using  
MODE input  
•
Threechipenableoptionforsimpledepthexpansion  
and address pipelining  
• Common data inputs and data outputs  
• JEDEC 100-Pin TQFP and  
119-pin PBGA package  
• Single +3.3V, +10%, –5% power supply  
• Power-down snooze mode  
• 3.3V I/O For SPS  
Write cycles are internally self-timed and are initiated by the  
rising edge of the clock input. Write cycles can be from one  
to four bytes wide as controlled by the write control inputs.  
Separate byte enables allow individual bytes to be written.  
Byte write operation is performed by using byte write  
enable (BWE).input combined with one or more individual  
byte write signals (BWx). In addition, Global Write (GW)  
is available for writing all bytes at one time, regardless of  
the byte write controls.  
• 2.5V I/O For LPS  
• Single cycle deselect  
• Snooze MODE for reduced-power standby  
• T version (three chip selects)  
• D version (two chip selects)  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
input pins. Subsequent burst addresses can be generated  
internally and controlled by the ADV (burst address  
advance) input pin.  
The mode pin is used to select the burst sequence order,  
LinearburstisachievedwhenthispinistiedLOW. Interleave  
burst is achieved when this pin is tied HIGH or left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
-166*  
3.5  
6
-150  
3.8  
-133  
4
-5  
5
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
6.7  
7.5  
133  
10  
100  
ns  
Frequency  
166  
150  
MHz  
*This speed available only in SPS version  
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the  
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
PRELIMINARY INFORMATION Rev. 00A  
1
04/17/01  
1234567...22

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与IS61LPS25636D-5TQ相关器件

型号 品牌 获取价格 描述 数据表
IS61LPS25636J-166BI ISSI

获取价格

 		Cache SRAM, 256KX36, 3.5ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61LPS25636J-200B ISSI

获取价格

 		Cache SRAM, 256KX36, 3.1ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61LPS25636J-225B ISSI

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 		Cache SRAM, 256KX36, 2.8ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61LPS25636T-225TQI ISSI

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 		Cache SRAM, 256KX36, 2.8ns, CMOS, PQFP100, TQFP-100
IS61LPS25636T-250TQ ISSI

获取价格

 		Cache SRAM, 256KX36, 2.6ns, CMOS, PQFP100, TQFP-100
IS61LPS25636T-5TQ ISSI

获取价格

 		Cache SRAM, 256KX36, 5ns, CMOS, PQFP100, TQFP-100
IS61LPS25672A ISSI

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 		256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC
IS61LPS25672A-250B1 ISSI

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 		256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC
IS61LPS25672A-250B1I ISSI

获取价格

 		256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC
IS61LPS25672A-250B1L ISSI

获取价格

 		256Kx72,512Kx36,1024Kx18 18Mb SYNCHRONOUS PIPELINED,SINGLE CYCLE DESELECT STATIC RAM

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