IS43R32800B
8Mx32
PRELIMINARY INFORMATION
MAY 2008
256Mb DDR Synchronous DRAM
FEATURES
DESCRIPTION:
IS43R32800B is a 4-bank x 2,097,152-word x32bit
Double Data Rate Synchronous DRAM, with SSTL_2
interface. All control and address signals are referenced
to the rising edge of CLK. Input data is registered on
both edges of data strobe, and output data and data
strobe are referenced on both edges of CLK. The
IS43R32800B achieves very high speed clock rate up to
200 MHz. It is packaged in 144-ball FBGA.
•ꢀ Vd d /Vd d q =2.5V+0.2V (-5, -6, -75)
•ꢀ Double data rate architecture; two data transfers
per clock cycle
•ꢀ Bidirectional, data strobe (DQS) is transmitted/
received with data
•ꢀ Differential clock input (CLK and /CLK)
•ꢀ DLL aligns DQ and DQS transitions with CLK
transitions edges of DQS
•ꢀ Commands entered on each positive CLK edge;
•ꢀ Data and data mask referenced to both edges of
KEY TIMING PARAMETERS
DQS
Parameter
-5
-6
-75 Unit
•ꢀ 4 bank operation controlled by BA0, BA1 (Bank
Clk Cycle Time
Address)
CAS Latency = 3
CAS Latency = 2.5
CAS Latency = 2
5
5
7.5
6
6
7.5
7.5
7.5
7.5
ns
ns
ns
•ꢀ /CAS latency –2.0/2.5/3.0 (programmable)
•ꢀ Burst length - 2/4/8 (programmable)
•ꢀ Burst type - Sequential/ Interleave (program-
Clk Frequency
mable)
CAS Latency = 3
CAS Latency = 2.5
CAS Latency = 2
200
200
143
167
167
143
143 MHz
143 MHz
143 MHz
•ꢀ Auto precharge / All bank precharge controlled
by A8
Access Time from Clock
CAS Latency = 3
•ꢀ 4096 refresh cycles/ 64ms (4 banks concurrent
+0.70 +0.70 +0.70 ns
refresh)
CAS Latency = 2.5 +0.70 +0.70 +0.70 ns
CAS Latency = 2 +0.75 +0.75 +0.70 ns
•ꢀ Auto refresh and Self refresh
•ꢀ Row address A0-11/ Column address A0-7, A9-
SSTL_2 Interface
•ꢀ Package 144-ball FBGA
•ꢀ Available in Industrial Temperature
•ꢀ Temperature Range:
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
ADDRESS TABLE
Parameter
8M x 32
Configuration
2M x 32 x 4 banks
BA0, BA1
Bank Address Pins
Autoprecharge Pins
Row Addresses
Column Addresses
Refresh Count
A8/AP
A0 – A11
A0 – A7, A9
4096 / 64ms
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. 00D
03/19/08