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IS43R83200A-75T PDF预览

IS43R83200A-75T

更新时间: 2024-10-27 15:35:31
品牌 Logo 应用领域
美国芯成 - ISSI 时钟动态存储器双倍数据速率光电二极管内存集成电路
页数 文件大小 规格书
36页 975K
描述
DDR DRAM, 32MX8, 0.75ns, CMOS, PDSO66, 0.400 INCH X 0.875 INCH, 0.65 MM PITCH, TSOP2-66

IS43R83200A-75T 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSOP2
包装说明:SOP, TSSOP66,.46针数:66
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.24风险等级:5.75
访问模式:FOUR BANK PAGE BURST最长访问时间:0.75 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):133 MHz
I/O 类型:COMMON交错的突发长度:2,4,8
JESD-30 代码:R-PDSO-G66JESD-609代码:e0
内存密度:268435456 bit内存集成电路类型:DDR DRAM
内存宽度:8湿度敏感等级:3
功能数量:1端口数量:1
端子数量:66字数:33554432 words
字数代码:32000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32MX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:TSSOP66,.46封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2.5 V认证状态:Not Qualified
刷新周期:8192自我刷新:YES
连续突发长度:2,4,8最大待机电流:0.006 A
子类别:DRAMs最大压摆率:0.17 mA
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

IS43R83200A-75T 数据手册

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®
IS43R83200A -6,-75 (4-bank x 8,388,608 - word x 8-bit)  
IS43R16160A -6,-75 (4-bank x 4,194,304 - word x 16-bit)  
ISSI  
256 Mb DDR Synchronous DRAM  
May 2005  
DESCRIPTION  
Input data is registered on both edges of data strob ,  
and output data and data strobe are referenced on  
IS43R83200A is a 4-bank x 8,388,608-word x 8bit,  
IS43R16160A is a 4-bank x 4,194,304-word x 16bit double  
data rate synchronous DRAM, with SSTL_2 interface.  
All control and address signals are referenced to the rising  
edge of CLK.  
both edges of CLK.  
The IS43R83200A/16160A achieves high speed clock  
rate up to 166 MHz .  
FEATURES  
- Vdd=Vddq=2.5V ꢀ.2V ꢁpowe ꢂsꢁꢁꢃl ꢄpe -ꢅ6-ꢆ5.  
- Double data rate architecture ; two data transfers per clock cycle.  
- Bidirectional, data strob (DQS) is transmitted/received with data  
- Differential clock input (CLK and /CLK)  
- DLL aligns DQ and DQS transitions with CLK transitions edges of DQS  
- Commands entered on each positive CLK edge ;  
- Data and data mask referenced to both edges of DQS  
- 4 bank operation controlled by BA0 , BA1 (Bank Address)  
- /CAS latency - 2.0 / 2.5/ 3 (programmable) ;  
Burst length - 2 / 4 / 8 (programmable)  
Burst type - Sequential / Interleave (programmable)  
- Auto precharge / All bank precharge controlled by A10  
- 8192 refresh cycles / 64ms (4 banks concurrent refresh)  
- Auto refresh and Self refresh  
- Row address A0-12 / Column address A0-9(x8)  
/A0-8(x16)  
- SSTL_2 Interface  
- Package  
400-mil, 66-pin Thin Small Outline Package (TSOP II)  
with 0.65mm lead pitch  
- JEDEC standard for -6 , -75  
- Lwad-ꢄeww avaiꢃabꢃw  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
1
05/13/05  

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