IS43R83200F
IS43/46R16160F, IS43/46R32800F
PRELIMINARY INFORMATION
MARCH 2014
8Mx32, 16Mx16, 32Mx8
256Mb DDR SDRAM
FEATURES
DEVICE OVERVIEW
•ꢀ VDDꢀandꢀVDDQ:ꢀ2.5Vꢀ±ꢀ0.2Vꢀ
•ꢀ SSTL_2ꢀcompatibleꢀI/O
ISSI’sꢀ256-MbitꢀDDRꢀSDRAMꢀachievesꢀhighꢀspeedꢀdataꢀ
transfer using pipeline architecture and two data word
accessesꢀperꢀclockꢀcycle.ꢀTheꢀ268,435,456-bitꢀmemoryꢀ
arrayꢀisꢀinternallyꢀorganizedꢀasꢀfourꢀbanksꢀofꢀ64Mbꢀtoꢀ
allowꢀconcurrentꢀoperations.ꢀTheꢀpipelineꢀallowsꢀReadꢀ
and Write burst accesses to be virtually continuous, with
theꢀoptionꢀtoꢀconcatenateꢀorꢀtruncateꢀtheꢀbursts.ꢀTheꢀ
programmable features of burst length, burst sequence
andꢀCASꢀlatencyꢀenableꢀfurtherꢀadvantages.ꢀTheꢀdeviceꢀ
isꢀavailableꢀinꢀ8-bit,ꢀ16-bitꢀandꢀ32-bitꢀdataꢀwordꢀsizeꢀ
InputꢀdataꢀisꢀregisteredꢀonꢀtheꢀI/Oꢀpinsꢀonꢀbothꢀedgesꢀ
ofꢀDataꢀStrobeꢀsignal(s),ꢀwhileꢀoutputꢀdataꢀisꢀreferencedꢀ
toꢀbothꢀedgesꢀofꢀDataꢀStrobeꢀandꢀbothꢀedgesꢀofꢀCLK.ꢀ
CommandsꢀareꢀregisteredꢀonꢀtheꢀpositiveꢀedgesꢀofꢀCLK.ꢀ
•ꢀ Double-dataꢀrateꢀarchitecture;ꢀtwoꢀdataꢀtransfersꢀ
per clock cycle
•ꢀ Bidirectional,ꢀdataꢀstrobeꢀ(DQS)ꢀisꢀtransmitted/
received with data, to be used in capturing data
at the receiver
•ꢀ DQSꢀisꢀedge-alignedꢀwithꢀdataꢀforꢀREADsꢀandꢀ
centre-alignedꢀwithꢀdataꢀforꢀWRITEs
•ꢀ Differentialꢀclockꢀinputsꢀ(CKꢀandꢀCK)
•ꢀ DLLꢀalignsꢀDQꢀandꢀDQSꢀtransitionsꢀwithꢀCKꢀ
transitions
•ꢀ CommandsꢀenteredꢀonꢀeachꢀpositiveꢀCKꢀedge;ꢀdataꢀ
andꢀdataꢀmaskꢀreferencedꢀtoꢀbothꢀedgesꢀofꢀDQS
•ꢀ Fourꢀinternalꢀbanksꢀforꢀconcurrentꢀoperation
AnꢀAutoꢀRefreshꢀmodeꢀisꢀprovided,ꢀalongꢀwithꢀaꢀSelfꢀ
Refreshꢀmode.ꢀAllꢀI/OsꢀareꢀSSTL_2ꢀcompatible.
•ꢀ DataꢀMaskꢀforꢀwriteꢀdata.ꢀDMꢀmasksꢀwriteꢀdataꢀ
ADDRESS TABLE
at both rising and falling edges of data strobe
Parameter
8M x 32
16M x 16
32M x 8
•ꢀ BurstꢀLength:ꢀ2,ꢀ4ꢀandꢀ8
•ꢀ BurstꢀType:ꢀSequentialꢀandꢀInterleaveꢀmode
•ꢀ ProgrammableꢀCASꢀlatency:ꢀ2,ꢀ2.5ꢀandꢀ3ꢀ
•ꢀ AutoꢀRefreshꢀandꢀSelfꢀRefreshꢀModes
•ꢀ AutoꢀPrecharge
Configuration 2Mꢀxꢀ32ꢀxꢀ4ꢀ
4Mꢀxꢀ16ꢀxꢀ4ꢀ
banks
8Mꢀxꢀ8ꢀxꢀ4ꢀ
banks
banks
BankꢀAddressꢀ BA0,ꢀBA1
Pins
BA0,ꢀBA1
BA0,ꢀBA1
Autoprecharge A8/AP
Pins
A10/AP
A10/AP
•ꢀ TRASꢀLockoutꢀsupportedꢀ(tRAP = tRCD)
RowꢀAddress 4K(A0ꢀ–ꢀA11) 8K(A0ꢀ–ꢀA12) 8K(A0ꢀ–ꢀA12)
OPTIONS
Column
Address
512(A0ꢀ–ꢀA7,ꢀ 512(A0ꢀ–ꢀA8) 1K(A0ꢀ–ꢀA9)
A9)
•ꢀ Configuration(s):ꢀ8Mx32,ꢀ16Mx16,ꢀ32Mx8
•ꢀ Package(s):ꢀ
ꢀ 144ꢀBallꢀBGAꢀ(x32)
66-pinꢀTSOP-IIꢀ(x8,ꢀx16)ꢀandꢀ60ꢀBallꢀBGAꢀ(x8,ꢀx16)
•ꢀ Lead-freeꢀpackageꢀavailable
•ꢀ TemperatureꢀRange:ꢀ
RefreshꢀCount
Com./Ind./A1 4Kꢀ/ꢀ64ms
A2 4Kꢀ/ꢀ16ms
8Kꢀ/ꢀ64ms
8Kꢀ/ꢀ16ms
8Kꢀ/ꢀ64ms
KEY TIMING PARAMETERS
ꢀ Commercialꢀ(0°Cꢀtoꢀ+70°C)
Speed Grade
-5
-6
Units
ꢀ Industrialꢀ(-40°Cꢀtoꢀ+85°C)
Automotive,ꢀA1ꢀ(-40°Cꢀtoꢀ+85°C)
Automotive,ꢀA2ꢀ(-40°Cꢀtoꢀ+105°C)
FCkꢀMaxꢀCLꢀ=ꢀ3ꢀ
FCkꢀMaxꢀCLꢀ=ꢀ2.5ꢀ
FCkꢀMaxꢀCLꢀ=ꢀ2ꢀ
200ꢀ
167ꢀ
133ꢀ
167ꢀ
167ꢀ
133ꢀ
ꢀ MHz
ꢀ MHz
ꢀ MHz
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest
version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.
1
Rev. 0A
03/24/2014
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