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IS43R32800D-5BL-TR PDF预览

IS43R32800D-5BL-TR

更新时间: 2024-11-24 22:59:23
品牌 Logo 应用领域
美国芯成 - ISSI 时钟动态存储器双倍数据速率内存集成电路
页数 文件大小 规格书
32页 1016K
描述
IC DRAM 256M PARALLEL 144LFBGA

IS43R32800D-5BL-TR 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:FBGA, BGA144,12X12,32Reach Compliance Code:compliant
Factory Lead Time:8 weeks风险等级:5.75
最长访问时间:0.7 ns最大时钟频率 (fCLK):200 MHz
I/O 类型:COMMON交错的突发长度:2,4,8
JESD-30 代码:S-PBGA-B144内存密度:268435456 bit
内存集成电路类型:DDR DRAM内存宽度:32
端子数量:144字数:8388608 words
字数代码:8000000最高工作温度:70 °C
最低工作温度:组织:8MX32
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:FBGA封装等效代码:BGA144,12X12,32
封装形状:SQUARE封装形式:GRID ARRAY, FINE PITCH
电源:2.5 V认证状态:Not Qualified
刷新周期:4096连续突发长度:2,4,8
最大待机电流:0.005 A子类别:DRAMs
最大压摆率:0.48 mA标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
Base Number Matches:1

IS43R32800D-5BL-TR 数据手册

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IS43R83200D  
IS43/46R16160D, IS43/46R32800D  
8Mx32,ꢀ16Mx16,ꢀ32Mx8ꢀ  
256MbꢀDDRꢀSDRAM  
JUNEꢀ2012  
FEATURES  
DEVICEꢀOVERVIEW  
•ꢀ VDDꢀandꢀVDDQ:ꢀ2.5Vꢀ ꢀ0.2Vꢀ  
•ꢀ SSTL_2ꢀcompatibleꢀI/O  
•ꢀ Double-dataꢀrateꢀarchitecture;ꢀtwoꢀdataꢀtransfersꢀ  
perꢀclockꢀcycle  
•ꢀ Bidirectional,ꢀdataꢀstrobeꢀ(DQS)ꢀisꢀtransmitted/  
receivedꢀwithꢀdata,ꢀtoꢀbeꢀusedꢀinꢀcapturingꢀdataꢀ  
atꢀtheꢀreceiver  
•ꢀ DQSꢀisꢀedge-alignedꢀwithꢀdataꢀforꢀREADsꢀandꢀ  
centre-alignedꢀwithꢀdataꢀforꢀWRITEs  
•ꢀ Differentialꢀclockꢀinputsꢀ(CKꢀandꢀCK)  
•ꢀ DLLꢀalignsꢀDQꢀandꢀDQSꢀtransitionsꢀwithꢀCKꢀ  
transitions  
•ꢀ CommandsꢀenteredꢀonꢀeachꢀpositiveꢀCKꢀedge;ꢀdataꢀ  
andꢀdataꢀmaskꢀreferencedꢀtoꢀbothꢀedgesꢀofꢀDQS  
•ꢀ Fourꢀinternalꢀbanksꢀforꢀconcurrentꢀoperation  
ISSI’sꢀ256-MbitꢀDDRꢀSDRAMꢀachievesꢀhighꢀspeedꢀdataꢀ  
transferꢀusingꢀpipelineꢀarchitectureꢀandꢀtwoꢀdataꢀwordꢀ  
accessesꢀperꢀclockꢀcycle.ꢀTheꢀ268,435,456-bitꢀmemoryꢀ  
arrayꢀisꢀinternallyꢀorganizedꢀasꢀfourꢀbanksꢀofꢀ64Mbꢀtoꢀ  
allowꢀconcurrentꢀoperations.ꢀTheꢀpipelineꢀallowsꢀReadꢀ  
andꢀWriteꢀburstꢀaccessesꢀtoꢀbeꢀvirtuallyꢀcontinuous,ꢀwithꢀ  
theꢀoptionꢀtoꢀconcatenateꢀorꢀtruncateꢀtheꢀbursts.ꢀTheꢀ  
programmableꢀfeaturesꢀofꢀburstꢀlength,ꢀburstꢀsequenceꢀ  
andꢀCASꢀlatencyꢀenableꢀfurtherꢀadvantages.ꢀTheꢀdeviceꢀ  
isꢀavailableꢀinꢀ8-bit,ꢀ16-bitꢀandꢀ32-bitꢀdataꢀwordꢀsizeꢀ  
InputꢀdataꢀisꢀregisteredꢀonꢀtheꢀI/Oꢀpinsꢀonꢀbothꢀedgesꢀ  
ofꢀDataꢀStrobeꢀsignal(s),ꢀwhileꢀoutputꢀdataꢀisꢀreferencedꢀ  
toꢀbothꢀedgesꢀofꢀDataꢀStrobeꢀandꢀbothꢀedgesꢀofꢀCLK.ꢀ  
CommandsꢀareꢀregisteredꢀonꢀtheꢀpositiveꢀedgesꢀofꢀCLK.ꢀ  
AnꢀAutoꢀRefreshꢀmodeꢀisꢀprovided,ꢀalongꢀwithꢀaꢀSelfꢀ  
Refreshꢀmode.ꢀAllꢀI/OsꢀareꢀSSTL_2ꢀcompatible.  
•ꢀ DataꢀMaskꢀforꢀwriteꢀdata.ꢀDMꢀmasksꢀwriteꢀdataꢀ  
atꢀbothꢀrisingꢀandꢀfallingꢀedgesꢀofꢀdataꢀstrobe  
ADDRESSTABLE  
Parameter  
8Mꢀxꢀ32  
16Mꢀxꢀ16  
32Mꢀxꢀ8  
•ꢀ BurstꢀLength:ꢀ2,ꢀ4ꢀandꢀ8  
•ꢀ BurstꢀType:ꢀSequentialꢀandꢀInterleaveꢀmode  
•ꢀ ProgrammableꢀCASꢀlatency:ꢀ2,ꢀ2.5ꢀandꢀ3ꢀ  
•ꢀ AutoꢀRefreshꢀandꢀSelfꢀRefreshꢀModes  
•ꢀ AutoꢀPrecharge  
Configuration 2Mꢀxꢀ32ꢀxꢀ4ꢀ  
banks  
4Mꢀxꢀ16ꢀxꢀ4ꢀꢀ 8Mꢀxꢀ8ꢀxꢀ4ꢀꢀ  
banks  
banks  
BankꢀAddressꢀ BA0,ꢀBA1  
Pins  
BA0,ꢀBA1  
BA0,ꢀBA1  
Autoprechargeꢀ A8/AP  
Pins  
A10/AP  
A10/AP  
•ꢀ TRASꢀLockoutꢀsupportedꢀ(tRAPꢀ=ꢀtRCD)  
RowꢀAddress 4K(A0ꢀ–ꢀA11) 8K(A0ꢀ–ꢀA12) 8K(A0ꢀ–ꢀA12)  
OPTIONS  
Columnꢀ  
Address  
512(A0ꢀ–ꢀA7,ꢀ 512(A0ꢀ–ꢀA8) 1K(A0ꢀ–ꢀA9)  
A9)  
•ꢀ Configuration(s):ꢀ8Mx32,ꢀ16Mx16,ꢀ32Mx8  
•ꢀ Package(s):ꢀ  
ꢀ 144ꢀBallꢀBGAꢀ(x32)  
RefreshꢀCountꢀ  
Com./Ind./A1ꢀ 4Kꢀ/ꢀ64msꢀ  
A2 4Kꢀ/ꢀ16ms  
8Kꢀ/ꢀ64msꢀ  
8Kꢀ/ꢀ16ms  
8Kꢀ/ꢀ64ms  
66-pinꢀTSOP-IIꢀ(x8,ꢀx16)ꢀandꢀ60ꢀBallꢀBGAꢀ(x8,ꢀx16)  
•ꢀ Lead-freeꢀpackageꢀavailable  
•ꢀ TemperatureꢀRange:ꢀ  
ꢀ Commercialꢀ(0°Cꢀtoꢀ+70°C)  
KEYTIMINGꢀPARAMETERS  
SpeedꢀGradeꢀ  
-5ꢀ  
-6ꢀ  
Unitsꢀ  
ꢀ Industrialꢀ(-40°Cꢀtoꢀ+85°C)ꢀ  
Automotive,ꢀA1ꢀ(-40°Cꢀtoꢀ+85°C)ꢀ  
Automotive,ꢀA2ꢀ(-40°Cꢀtoꢀ+105°C)  
F
F
F
CkꢀMaxꢀCLꢀ=ꢀ3ꢀ  
CkꢀMaxꢀCLꢀ=ꢀ2.5ꢀ  
CkꢀMaxꢀCLꢀ=ꢀ2ꢀ  
200ꢀ  
200ꢀ  
133ꢀ  
167ꢀ  
167ꢀ  
133ꢀ  
ꢀ MHz  
ꢀ MHz  
ꢀ MHz  
Copyrightꢀ©ꢀ2012ꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀꢀAllꢀrightsꢀreserved.ꢀꢀISSIꢀreservesꢀtheꢀrightꢀtoꢀmakeꢀchangesꢀtoꢀthisꢀspecificationꢀandꢀitsꢀproductsꢀatꢀanyꢀtimeꢀwithoutꢀ  
notice.ꢀꢀꢀISSIꢀassumesꢀnoꢀliabilityꢀarisingꢀoutꢀofꢀtheꢀapplicationꢀorꢀuseꢀofꢀanyꢀinformation,ꢀproductsꢀorꢀservicesꢀdescribedꢀherein.ꢀCustomersꢀareꢀadvisedꢀtoꢀobtainꢀtheꢀlat-  
estꢀversionꢀofꢀthisꢀdeviceꢀspecificationꢀbeforeꢀrelyingꢀonꢀanyꢀpublishedꢀinformationꢀandꢀbeforeꢀplacingꢀordersꢀforꢀproducts.ꢀꢀ  
IntegratedꢀSiliconꢀSolution,ꢀInc.ꢀdoesꢀnotꢀrecommendꢀtheꢀuseꢀofꢀanyꢀofꢀitsꢀproductsꢀinꢀlifeꢀsupportꢀapplicationsꢀwhereꢀtheꢀfailureꢀorꢀmalfunctionꢀofꢀtheꢀproductꢀcanꢀreason-  
ablyꢀbeꢀexpectedꢀtoꢀcauseꢀfailureꢀofꢀtheꢀlifeꢀsupportꢀsystemꢀorꢀtoꢀsignificantlyꢀaffectꢀitsꢀsafetyꢀorꢀeffectiveness.ꢀProductsꢀareꢀnotꢀauthorizedꢀforꢀuseꢀinꢀsuchꢀapplicationsꢀ  
unlessꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀreceivesꢀwrittenꢀassuranceꢀtoꢀitsꢀsatisfaction,ꢀthat:  
a.)ꢀtheꢀriskꢀofꢀinjuryꢀorꢀdamageꢀhasꢀbeenꢀminimized;  
b.)ꢀtheꢀuserꢀassumeꢀallꢀsuchꢀrisks;ꢀand  
c.)ꢀpotentialꢀliabilityꢀofꢀIntegratedꢀSiliconꢀSolution,ꢀIncꢀisꢀadequatelyꢀprotectedꢀunderꢀtheꢀcircumstances  
Integrated Silicon Solution, Inc. ꢀ  
1
Rev.ꢀ B  
06/19/2012  

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