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IS42S16400J-7TLI-TR PDF预览

IS42S16400J-7TLI-TR

更新时间: 2024-09-17 20:47:23
品牌 Logo 应用领域
美国芯成 - ISSI 时钟动态存储器光电二极管内存集成电路
页数 文件大小 规格书
60页 1383K
描述
Synchronous DRAM, 4MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, ROHS COMPLIANT, TSOP2-54

IS42S16400J-7TLI-TR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSOP2
包装说明:TSOP2, TSOP54,.46,32针数:54
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.02Factory Lead Time:6 weeks
风险等级:5.26访问模式:FOUR BANK PAGE BURST
最长访问时间:5.4 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):143 MHzI/O 类型:COMMON
交错的突发长度:1,2,4,8JESD-30 代码:R-PDSO-G54
JESD-609代码:e3长度:22.22 mm
内存密度:67108864 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:16湿度敏感等级:3
功能数量:1端口数量:1
端子数量:54字数:4194304 words
字数代码:4000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:4MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP54,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
刷新周期:4096座面最大高度:1.2 mm
自我刷新:YES连续突发长度:1,2,4,8,FP
最大待机电流:0.002 A子类别:DRAMs
最大压摆率:0.13 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL处于峰值回流温度下的最长时间:10
宽度:10.16 mmBase Number Matches:1

IS42S16400J-7TLI-TR 数据手册

 浏览型号IS42S16400J-7TLI-TR的Datasheet PDF文件第2页浏览型号IS42S16400J-7TLI-TR的Datasheet PDF文件第3页浏览型号IS42S16400J-7TLI-TR的Datasheet PDF文件第4页浏览型号IS42S16400J-7TLI-TR的Datasheet PDF文件第5页浏览型号IS42S16400J-7TLI-TR的Datasheet PDF文件第6页浏览型号IS42S16400J-7TLI-TR的Datasheet PDF文件第7页 
IS42S16400J  
IS45S16400J  
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)  
SYNCHRONOUS DYNAMIC RAM  
JULY 2014  
FEATURES  
OVERVIEW  
ISSI's64MbSynchronousDRAMisorganizedas1,048,576ꢀ  
bitsꢀ xꢀ 16-bitꢀ xꢀ 4-bankꢀ forꢀ improvedꢀ performance.ꢀ Theꢀ  
synchronousꢀ DRAMsꢀ achieveꢀ high-speedꢀ dataꢀ transferꢀ  
using pipeline architecture. All inputs and outputs signals  
refer to the rising edge of the clock input.  
•ꢀ Clock frequency: 200, 166, 143, 133 MHz  
•ꢀ Fullyꢀsynchronous;ꢀallꢀsignalsꢀreferencedꢀtoꢀaꢀ  
positive clock edge  
•ꢀ Internalꢀbankꢀforꢀhidingꢀrowꢀaccess/precharge  
•ꢀ Singleꢀ3.3Vꢀpowerꢀsupply  
•ꢀ LVTTLꢀinterface  
•ꢀ Programmableꢀburstꢀlengthꢀ  
KEY TIMING PARAMETERS  
– (1, 2, 4, 8, full page)  
•ꢀ Programmableꢀburstꢀsequence:ꢀ  
Parameter  
-5  
-6  
-7  
Unit  
Sequential/Interleave  
ClkꢀCycleꢀTimeꢀ  
CASꢀLatencyꢀ=ꢀ3ꢀ  
CASꢀLatencyꢀ=ꢀ2ꢀ  
ꢀꢀ  
5ꢀ  
7.5ꢀ  
6ꢀ  
7.5ꢀ  
7ꢀ  
7.5ꢀ  
nsꢀ  
ns  
•ꢀ Selfꢀrefreshꢀmodes  
•ꢀ Autoꢀrefreshꢀ(CBR)  
ClkꢀFrequencyꢀ  
CASꢀLatencyꢀ=ꢀ3ꢀ  
CASꢀLatencyꢀ=ꢀ2ꢀ  
ꢀꢀ  
200ꢀ  
133ꢀ  
•ꢀ 4096ꢀrefreshꢀcyclesꢀeveryꢀ64ꢀmsꢀ(Com,ꢀInd,ꢀA1ꢀ  
166ꢀ  
133ꢀ  
143ꢀ  
133ꢀ  
Mhzꢀ  
Mhz  
grade) or 16ms (A2 grade)  
•ꢀ Randomꢀcolumnꢀaddressꢀeveryꢀclockꢀcycle  
AccessꢀTimeꢀꢀfromꢀClockꢀ  
CASꢀLatencyꢀ=ꢀ3ꢀ  
CASꢀLatencyꢀ=ꢀ2ꢀ  
4.8ꢀ  
5.4ꢀ  
5.4ꢀ  
5.4ꢀ  
5.4ꢀ  
5.4ꢀ  
nsꢀ  
ns  
•ꢀ ProgrammableꢀCAS latency (2, 3 clocks)  
•ꢀ Burstꢀread/writeꢀandꢀburstꢀread/singleꢀwriteꢀ  
operations capability  
•ꢀ Burstꢀterminationꢀbyꢀburstꢀstopꢀandꢀprechargeꢀ  
command  
ADDRESS TABLE  
OPTIONS  
Parameter  
4M x 16  
•ꢀ Package:  
Configuration  
1M x 16 x 4  
54-pinꢀTSOPꢀII  
banks  
54-ballꢀTF-BGAꢀ(8mmꢀxꢀ8mm)  
60-ballꢀTF-BGAꢀ(10.1mmꢀxꢀ6.4mm)  
Refresh Count  
Com./Ind. 4K/64ms  
A1 4K/64ms  
•ꢀ OperatingꢀTemperatureꢀRange  
Commercial (0oC to +70oC)  
A2 4K/16ms  
Industrial (-40oC to +85oC)  
Row Addresses  
A0-A11  
AutomotiveꢀGradeꢀA1ꢀ(-40oC to +85oC)  
AutomotiveꢀGradeꢀA2ꢀ(-40oC to +105oC)  
Column Addresses  
Bank Address Pins  
Auto Precharge Pins  
A0-A7  
BA0, BA1  
A10/AP  
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no  
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on  
any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-  
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon  
Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc. — www.issi.com  
1
Rev. G  
7/30/2014  

IS42S16400J-7TLI-TR 替代型号

型号 品牌 替代类型 描述 数据表
IS42S16400J-7TL ISSI

类似代替

IC DRAM 64M PARALLEL 54TSOP
IS42S16400J-7TLI ISSI

类似代替

Synchronous DRAM, 4MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, ROHS COMPLIANT, TSOP2-54
IS42S16400J-6TL ISSI

类似代替

1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

与IS42S16400J-7TLI-TR相关器件

型号 品牌 获取价格 描述 数据表
IS42S16400J-7TL-TR ISSI

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IC DRAM 64M PARALLEL 54TSOP
IS42S16400L ICSI

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2(1)M words x 8(16) bits x 4 banks (64-mbit) synchronous dynamic ram
IS42S16400L-10T ISSI

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Synchronous DRAM, 4MX16, 7ns, CMOS, PDSO54, 0.400 INCH, TSOP2-54
IS42S16400L-10TI ISSI

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Synchronous DRAM, 4MX16, 7ns, CMOS, PDSO54, 0.400 INCH, TSOP2-54
IS42S16400L-6T ISSI

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Synchronous DRAM, 4MX16, 5.5ns, CMOS, PDSO54, 0.400 INCH, TSOP2-54
IS42S16400L-7T ISSI

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Synchronous DRAM, 4MX16, 6ns, CMOS, PDSO54, 0.400 INCH, TSOP2-54
IS42S16400L-7TI ICSI

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Synchronous DRAM, 4MX16, 5.4ns, CMOS, PDSO54,
IS42S16400L-7TI ISSI

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Synchronous DRAM, 4MX16, 6ns, CMOS, PDSO54, 0.400 INCH, TSOP2-54
IS42S16400L-8T ICSI

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Synchronous DRAM, 4MX16, 6ns, CMOS, PDSO54,
IS42S16400L-8T ISSI

获取价格

Synchronous DRAM, 4MX16, 6ns, CMOS, PDSO54, 0.400 INCH, TSOP2-54