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IS42S16800-5TLI PDF预览

IS42S16800-5TLI

更新时间: 2024-11-27 18:52:07
品牌 Logo 应用领域
美国芯成 - ISSI 时钟动态存储器光电二极管内存集成电路
页数 文件大小 规格书
61页 814K
描述
Synchronous DRAM, 8MX16, 5ns, CMOS, PDSO54, 0.400 MM INCH, LEAD FREE, TSOP2-54

IS42S16800-5TLI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSOP2
包装说明:TSOP2, TSOP54,.46,32针数:54
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.02风险等级:5.36
访问模式:FOUR BANK PAGE BURST最长访问时间:5 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):200 MHz
I/O 类型:COMMON交错的突发长度:1,2,4,8
JESD-30 代码:R-PDSO-G54JESD-609代码:e3
长度:22.22 mm内存密度:134217728 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:16
湿度敏感等级:3功能数量:1
端口数量:1端子数量:54
字数:8388608 words字数代码:8000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:-40 °C组织:8MX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装等效代码:TSOP54,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified刷新周期:4096
座面最大高度:1.2 mm自我刷新:YES
连续突发长度:1,2,4,8,FP最大待机电流:0.002 A
子类别:DRAMs最大压摆率:0.2 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:10.16 mm
Base Number Matches:1

IS42S16800-5TLI 数据手册

 浏览型号IS42S16800-5TLI的Datasheet PDF文件第2页浏览型号IS42S16800-5TLI的Datasheet PDF文件第3页浏览型号IS42S16800-5TLI的Datasheet PDF文件第4页浏览型号IS42S16800-5TLI的Datasheet PDF文件第5页浏览型号IS42S16800-5TLI的Datasheet PDF文件第6页浏览型号IS42S16800-5TLI的Datasheet PDF文件第7页 
IS42S81600  
IS42S16800  
16M x 8, 8M x16  
MARCH 2009  
128Mb SYNCHRONOUS DRAM  
OVERVIEW  
FEATURES  
ISSI'sꢀ128MbꢀSynchronousꢀDRAMꢀꢀachievesꢀhigh-speedꢀ  
data transfer using pipeline architecture. All inputs and  
outputs signals refer to the rising edge of the clock input.  
Theꢀ128MbꢀSDRAMꢀisꢀorganizedꢀasꢀfollows.ꢀ  
•ꢀ Clockꢀfrequency:ꢀ200,ꢀ166,ꢀ143,ꢀ133ꢀMHz  
•ꢀ Fullyꢀsynchronous;ꢀallꢀsignalsꢀreferencedꢀtoꢀaꢀ  
positive clock edge  
•ꢀ Internalꢀbankꢀforꢀhidingꢀrowꢀaccess/precharge  
•ꢀ Powerꢀsupply  
Vd d  
Vd d q  
IS42S81600ꢀ  
IS42S16800ꢀ  
IS42S81600ꢀ  
ꢀ IS42S16800ꢀ  
•ꢀ LVTTLꢀinterface  
ꢀ3.3Vꢀ 3.3Vꢀꢀ  
4Mꢀx8ꢀx4ꢀBanksꢀ 2Mꢀx16ꢀx4ꢀBanksꢀ  
ꢀ3.3Vꢀ 3.3Vꢀꢀ  
54-pinꢀTSOPIIꢀ  
54-pinꢀTSOPII  
54-ballꢀBGA  
•ꢀ Programmableꢀburstꢀlengthꢀ  
–ꢀ(1,ꢀ2,ꢀ4,ꢀ8,ꢀfullꢀpage)  
•ꢀ Programmableꢀburstꢀsequence:ꢀ  
Sequential/Interleaveꢀ  
•ꢀ AutoꢀRefreshꢀ(CBR)  
KEY TIMING PARAMETERS  
•ꢀ SelfꢀRefresh  
Parameter  
-5  
-6  
-7 -75E Unit  
•ꢀ 4096ꢀrefreshꢀcyclesꢀeveryꢀ64ꢀms  
•ꢀ Randomꢀcolumnꢀaddressꢀeveryꢀclockꢀcycle  
•ꢀ ProgrammableꢀCASꢀlatencyꢀ(2,ꢀ3ꢀclocks)  
ClkꢀCycleꢀTimeꢀ  
CASꢀLatencyꢀ=ꢀ3ꢀ  
CASꢀLatencyꢀ=ꢀ2ꢀ  
ꢀꢀ  
5ꢀ  
10ꢀ  
6ꢀ  
10ꢀ  
7ꢀ  
10ꢀ  
7.5ꢀ  
ns  
ns  
ClkꢀFrequencyꢀ  
CASꢀLatencyꢀ=ꢀ3ꢀ  
CASꢀLatencyꢀ=ꢀ2ꢀ  
ꢀꢀ  
200ꢀ  
100ꢀ  
•ꢀ Burstꢀread/writeꢀandꢀburstꢀread/singleꢀwriteꢀ  
166ꢀ  
100ꢀ  
143ꢀ  
100ꢀ  
133ꢀ  
Mhzꢀ  
Mhz  
operations capability  
•ꢀ Burstꢀterminationꢀbyꢀburstꢀstopꢀandꢀprechargeꢀ  
AccessꢀTimeꢀꢀfromꢀClockꢀ  
CASꢀLatencyꢀ=ꢀ3ꢀ  
CASꢀLatencyꢀ=ꢀ2ꢀ  
command  
5.0ꢀ  
6.5ꢀ  
5.4ꢀ  
6.5ꢀ  
5.4ꢀ  
6.5ꢀ  
5.5ꢀ  
ns  
ns  
•ꢀ IndustrialꢀꢀTemperatureꢀAvailability  
•ꢀ Lead-freeꢀAvailability  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-  
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain  
the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com  
1
Rev. A  
03/03/09  

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