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IS42S16800A-7B PDF预览

IS42S16800A-7B

更新时间: 2024-11-23 22:51:39
品牌 Logo 应用领域
矽成 - ICSI 动态存储器
页数 文件大小 规格书
66页 553K
描述
16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM

IS42S16800A-7B 数据手册

 浏览型号IS42S16800A-7B的Datasheet PDF文件第2页浏览型号IS42S16800A-7B的Datasheet PDF文件第3页浏览型号IS42S16800A-7B的Datasheet PDF文件第4页浏览型号IS42S16800A-7B的Datasheet PDF文件第5页浏览型号IS42S16800A-7B的Datasheet PDF文件第6页浏览型号IS42S16800A-7B的Datasheet PDF文件第7页 
IS42S81600A, IS42LS81600A  
IS42S16800A, IS42LS16800A  
IS42S32400A, IS42LS32400A  
®
ISSI  
16Meg x 8, 8Meg x16 & 4Meg x 32  
128-MBIT SYNCHRONOUS DRAM  
ADVANCED INFORMATION  
AUGUST 2002  
OVERVIEW  
FEATURES  
ISSI's 128Mb Synchronous DRAM achieves high-speed  
data transfer using pipeline architecture. All inputs and  
outputs signals refer to the rising edge of the clock  
input.The 128Mb SDARM is organized as follows.  
• Clock frequency: 133 100, MHz  
• Fully synchronous; all signals referenced to a  
positive clock edge  
• Internal bank for hiding row access/precharge  
• Power supply  
VDD  
VDDQ  
IS42LS81600A  
IS42S81600A  
4M x8x4 Banks  
54pin TSOPII  
IS42LS16800A  
IS42S16800A  
IS42LS32400A  
IS42S32400A  
IS42LS81600A  
IS42LS16800A  
2.5V 1.8V (2.5V tolerant)  
2.5V 1.8V (2.5V tolerant)  
2M x16x4 Banks 2M x16x4 Banks  
IS42LS32400A  
IS42S81600A  
2.5V 1.8V (2.5V tolerant)  
3.3V 3.3V  
54ballFBGA  
90ballFBGA  
86pin TSOPII  
54 pin TSOPII  
IS42S16800A  
IS42S32400A  
3.3V 3.3V  
3.3V 3.3V  
• LVTTL interface  
• Programmable burst length  
– (1, 2, 4, 8, full page)  
KEY TIMING PARAMETERS  
• Programmable burst sequence:  
Sequential/Interleave  
Parameter  
-7  
-10 Unit  
Clk Cycle Time  
CAS Latency = 3  
CAS Latency = 2  
• Extended Mode Register  
7
10  
10  
10  
ns  
ns  
• Programmable Power Reduction Feature by  
partial array activation during Self-Refresh  
Clk Frequency  
CAS Latency = 3  
CAS Latency = 2  
133  
100  
100  
100  
Mhz  
Mhz  
• Auto Refresh (CBR)  
• Temp. Compensated Self Refresh.  
• Self Refresh with programmable refresh periods  
• 4096 refresh cycles every 64 ms  
Access Time from Clock  
CAS Latency = 3  
5.4  
6
7
9
ns  
ns  
CAS Latency = 2  
Row to Column Delay Time (tRCD)  
Row Precharge Tim (tRP)  
15  
15  
18  
18  
ns  
ns  
• Random column address every clock cycle  
• Programmable CAS latency (2, 3 clocks)  
• Burst read/write and burst read/single write  
operations capability  
• Burst termination by burst stop and precharge  
command  
• Industrial Temperature Availability  
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any  
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are  
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
ADVANCEDINFORMATION,Rev. 00A  
1
08/01/02  

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