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IS42S16800A-6T PDF预览

IS42S16800A-6T

更新时间: 2024-11-26 22:51:39
品牌 Logo 应用领域
美国芯成 - ISSI 动态存储器
页数 文件大小 规格书
61页 536K
描述
16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM

IS42S16800A-6T 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:TSOP2,
针数:54Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.08访问模式:FOUR BANK PAGE BURST
最长访问时间:5.4 ns其他特性:AUTO/SELF REFRESH
JESD-30 代码:R-PDSO-G54JESD-609代码:e0
长度:22.22 mm内存密度:134217728 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:16
湿度敏感等级:3功能数量:1
端口数量:1端子数量:54
字数:8388608 words字数代码:8000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:8MX16
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1.2 mm自我刷新:YES
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10.16 mm
Base Number Matches:1

IS42S16800A-6T 数据手册

 浏览型号IS42S16800A-6T的Datasheet PDF文件第2页浏览型号IS42S16800A-6T的Datasheet PDF文件第3页浏览型号IS42S16800A-6T的Datasheet PDF文件第4页浏览型号IS42S16800A-6T的Datasheet PDF文件第5页浏览型号IS42S16800A-6T的Datasheet PDF文件第6页浏览型号IS42S16800A-6T的Datasheet PDF文件第7页 
IS42S81600A,  
IS42S16800A,  
IS42S32400A,  
®
ISSI  
16Meg x 8, 8Meg x16 & 4Meg x 32  
128-MBIT SYNCHRONOUS DRAM  
PRELIMINARY INFORMATION  
JANUARY 2005  
OVERVIEW  
FEATURES  
ISSI's 128Mb Synchronous DRAM achieves high-speed  
data transfer using pipeline architecture. All inputs and  
outputs signals refer to the rising edge of the clock  
input.The 128Mb SDRAM is organized as follows.  
• Clock frequency: 166,143,100 MHz  
• Fully synchronous; all signals referenced to a  
positive clock edge  
• Internal bank for hiding row access/precharge  
• Power supply  
VDD  
VDDQ  
IS42S81600A  
4M x8x4 Banks  
54-pin TSOPII  
IS42S16800A  
IS42S32400A  
IS42S81600A  
IS42S16800A  
3.3V 3.3V  
3.3V 3.3V  
3.3V 3.3V  
2M x16x4 Banks 1M x32x4 Banks  
54-pin TSOPII  
86-pin TSOPII  
IS42S32400A  
• LVTTL interface  
• Programmable burst length  
– (1, 2, 4, 8, full page)  
• Programmable burst sequence:  
Sequential/Interleave  
KEY TIMING PARAMETERS  
• Auto Refresh (CBR)  
• Self Refresh with programmable refresh periods  
• 4096 refresh cycles every 64 ms  
Parameter  
-6  
-7  
-10 Unit  
Clk Cycle Time  
CAS Latency = 3  
CAS Latency = 2  
6
-
7
10  
10  
10  
ns  
ns  
• Random column address every clock cycle  
• Programmable CAS latency (2, 3 clocks)  
Clk Frequency  
CAS Latency = 3  
CAS Latency = 2  
• Burst read/write and burst read/single write  
operations capability  
166  
-
143  
100  
100  
100  
Mhz  
Mhz  
• Burst termination by burst stop and precharge  
command  
Access Time from Clock  
CAS Latency = 3  
CAS Latency = 2  
5.4  
-
5.4  
6
7
9
ns  
ns  
• Industrial Temperature Availability  
• Lead-freeAvailability  
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any  
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are  
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
PRELIMINARYINFORMATION,Rev. 00C  
1
01/20/05  

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