Datasheet > IS42S16800D

IS42S16800D

更新时间： 2024-11-27 05:39:31

品牌	Logo	应用领域
美国芯成 - ISSI		动态存储器
页数	文件大小	规格书
62页	530K
描述
16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM

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IS42S16800D 数据手册

IS42S81600D

IS42S16800D

16Meg x 8, 8Meg x16

128-MBIT SYNCHRONOUS DRAM

JULY 2008

OVERVIEW

FEATURES

ISSI's 128Mb Synchronous DRAM achieves high-speed

data transfer using pipeline architecture. All inputs and

outputs signals refer to the rising edge of the clock

input.The 128Mb SDRAM is organized as follows.

• Clock frequency: 166, 143, 133 MHz

• Fully synchronous; all signals referenced to a

positive clock edge

• Internal bank for hiding row access/precharge

• Power supply

V^DD

3.3V 3.3V

VDDQ

IS42S81600D

4M x8x4 Banks

54-pin TSOPII

IS42S16800D

2M x16x4 Banks

54-pin TSOPII

54-ballBGA

IS42S81600D

IS42S16800D

3.3V 3.3V

• LVTTL interface

• Programmable burst length

– (1, 2, 4, 8, full page)

• Programmable burst sequence:

Sequential/Interleave

• Auto Refresh (CBR)

KEY TIMING PARAMETERS

• Self Refresh with programmable refresh periods

• 4096 refresh cycles every 64 ms

Parameter

-6

-7

-75E Unit

• Random column address every clock cycle

• Programmable CAS latency (2, 3 clocks)

Clk Cycle Time

CAS Latency = 3

CAS Latency = 2

—

7.5

• Burst read/write and burst read/single write

operations capability

Clk Frequency

CAS Latency = 3

CAS Latency = 2

166

125

143

100

—

133

Mhz

• Burst termination by burst stop and precharge

command

Access Time from Clock

CAS Latency = 3

CAS Latency = 2

• Industrial Temperature Availability

• Lead-freeAvailability

5.4

6.5

5.4

6.5

—

6.5

time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are

advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

07/28/08

12 3 4 5 6 7...62

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