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IS42S16800D-6BL PDF预览

IS42S16800D-6BL

更新时间: 2024-11-27 05:39:31
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路动态存储器时钟
页数 文件大小 规格书
62页 530K
描述
16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM

IS42S16800D-6BL 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:BGA包装说明:VFBGA, BGA54,9X9,32
针数:54Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.61Is Samacsys:N
访问模式:FOUR BANK PAGE BURST最长访问时间:5.4 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):166 MHz
I/O 类型:COMMON交错的突发长度:1,2,4,8
JESD-30 代码:R-PBGA-B54JESD-609代码:e1
长度:13 mm内存密度:134217728 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:16
湿度敏感等级:3功能数量:1
端口数量:1端子数量:54
字数:8388608 words字数代码:8000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:8MX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:VFBGA封装等效代码:BGA54,9X9,32
封装形状:RECTANGULAR封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified刷新周期:4096
座面最大高度:1 mm自我刷新:YES
连续突发长度:1,2,4,8,FP最大待机电流:0.001 A
子类别:DRAMs最大压摆率:0.18 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:40宽度:8 mm
Base Number Matches:1

IS42S16800D-6BL 数据手册

 浏览型号IS42S16800D-6BL的Datasheet PDF文件第2页浏览型号IS42S16800D-6BL的Datasheet PDF文件第3页浏览型号IS42S16800D-6BL的Datasheet PDF文件第4页浏览型号IS42S16800D-6BL的Datasheet PDF文件第5页浏览型号IS42S16800D-6BL的Datasheet PDF文件第6页浏览型号IS42S16800D-6BL的Datasheet PDF文件第7页 
IS42S81600D  
IS42S16800D  
16Meg x 8, 8Meg x16  
128-MBIT SYNCHRONOUS DRAM  
JULY 2008  
OVERVIEW  
FEATURES  
ISSI's 128Mb Synchronous DRAM achieves high-speed  
data transfer using pipeline architecture. All inputs and  
outputs signals refer to the rising edge of the clock  
input.The 128Mb SDRAM is organized as follows.  
• Clock frequency: 166, 143, 133 MHz  
• Fully synchronous; all signals referenced to a  
positive clock edge  
• Internal bank for hiding row access/precharge  
• Power supply  
VDD  
3.3V 3.3V  
VDDQ  
IS42S81600D  
4M x8x4 Banks  
54-pin TSOPII  
IS42S16800D  
2M x16x4 Banks  
54-pin TSOPII  
54-ballBGA  
IS42S81600D  
IS42S16800D  
3.3V 3.3V  
• LVTTL interface  
• Programmable burst length  
– (1, 2, 4, 8, full page)  
• Programmable burst sequence:  
Sequential/Interleave  
• Auto Refresh (CBR)  
KEY TIMING PARAMETERS  
• Self Refresh with programmable refresh periods  
• 4096 refresh cycles every 64 ms  
Parameter  
-6  
-7  
-75E Unit  
• Random column address every clock cycle  
• Programmable CAS latency (2, 3 clocks)  
Clk Cycle Time  
CAS Latency = 3  
CAS Latency = 2  
6
8
7
10  
7.5  
ns  
ns  
• Burst read/write and burst read/single write  
operations capability  
Clk Frequency  
CAS Latency = 3  
CAS Latency = 2  
166  
125  
143  
100  
133  
Mhz  
Mhz  
• Burst termination by burst stop and precharge  
command  
Access Time from Clock  
CAS Latency = 3  
CAS Latency = 2  
• Industrial Temperature Availability  
• Lead-freeAvailability  
5.4  
6.5  
5.4  
6.5  
6.5  
ns  
ns  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any  
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are  
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com  
1
Rev. E  
07/28/08  

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