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IS42S16400L-7TI PDF预览

IS42S16400L-7TI

更新时间: 2024-09-17 15:43:03
品牌 Logo 应用领域
矽成 - ICSI 时钟动态存储器光电二极管内存集成电路
页数 文件大小 规格书
68页 1489K
描述
Synchronous DRAM, 4MX16, 5.4ns, CMOS, PDSO54,

IS42S16400L-7TI 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:TSOP, TSOP54,.46,32Reach Compliance Code:unknown
风险等级:5.8最长访问时间:5.4 ns
最大时钟频率 (fCLK):133 MHzI/O 类型:COMMON
交错的突发长度:1,2,4,8JESD-30 代码:R-PDSO-G54
JESD-609代码:e0内存密度:67108864 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:16
端子数量:54字数:4194304 words
字数代码:4000000最高工作温度:85 °C
最低工作温度:组织:4MX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP封装等效代码:TSOP54,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
电源:3.3 V认证状态:Not Qualified
刷新周期:4096连续突发长度:1,2,4,8,FP
最大待机电流:0.001 A子类别:DRAMs
最大压摆率:0.07 mA标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUALBase Number Matches:1

IS42S16400L-7TI 数据手册

 浏览型号IS42S16400L-7TI的Datasheet PDF文件第2页浏览型号IS42S16400L-7TI的Datasheet PDF文件第3页浏览型号IS42S16400L-7TI的Datasheet PDF文件第4页浏览型号IS42S16400L-7TI的Datasheet PDF文件第5页浏览型号IS42S16400L-7TI的Datasheet PDF文件第6页浏览型号IS42S16400L-7TI的Datasheet PDF文件第7页 
IS42S8800/IS42S8800L  
IS42S16400/IS42S16400L  
2(1)M Words x 8(16) Bits x 4 Banks (64-MBIT)  
SYNCHRONOUS DYNAMIC RAM  
FEATURES  
DESCRIPTION  
The IS42S8800 and IS42S16400 are high-speed 67,  
108,864-bit synchronous dynamic random-access  
moeories, organized as 2,097,152 x 8 x 4 and 1,048,  
576 x 16 x 4 (word x bit x bank), respectively.  
• Single 3.3V (± 0.3V) power supply  
• High speed clock cycle time -7: 133MHz<3-3-3>,  
-8: 100MHz<2-2-2>  
• Fully synchronous operation referenced to clock  
rising edge  
The synchronous DRAMs achieved high-speed data  
transfer using the pipeline architecture and clock  
frequency up to 133MHz for -7. All input and outputs  
are synchronized with the postive edge of the clock.  
The synchronous DRAMs are compatible with Low  
Voltage TTL (LVTTL).These products are pack-aged  
in 54-pin TSOP-2.  
• Possible to assert random column access in  
every cycle  
• Quad internal banks contorlled by A12 & A13  
(Bank Select)  
• Byte control by LDQM and UDQM for  
IS42S16400  
• Programmable Wrap sequence (Sequential /  
Interleave)  
• Programmable burst length (1, 2, 4, 8 and full  
page)  
• Programmable /CAS latency (2 and 3)  
• Automatic precharge and controlled precharge  
• CBR (Auto) refresh and self refresh  
• X8, X16 organization  
• LVTTL compatible inputs and outputs  
• 4,096 refresh cycles / 64ms  
• Burst termination by Burst stop and Precharge  
command  
• Package 400mil 54-pin TSOP-2  
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors  
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.  
Integrated Circuit Solution Inc.  
DR007-0A  
1

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