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IS42S16400L-7T PDF预览

IS42S16400L-7T

更新时间: 2024-11-08 08:25:43
品牌 Logo 应用领域
美国芯成 - ISSI 动态存储器光电二极管
页数 文件大小 规格书
54页 561K
描述
Synchronous DRAM, 4MX16, 6ns, CMOS, PDSO54, 0.400 INCH, TSOP2-54

IS42S16400L-7T 数据手册

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®
IS42S16400L  
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)  
SYNCHRONOUS DYNAMIC RAM  
ISSI  
PRELIMINARY  
DECEMBER 2001  
FEATURES  
OVERVIEW  
ISSI's 64Mb Synchronous DRAM IS42S16400L is  
organized as 1,048,576 bits x 16-bit x 4-bank for improved  
performance.ThesynchronousDRAMsachievehigh-speed  
data transfer using pipeline architecture. All inputs and  
outputs signals refer to the rising edge of the clock input.  
• Clock frequency: 166, 133, 100 MHz  
• Fully synchronous; all signals referenced to a  
positive clock edge  
• Internal bank for hiding row access/precharge  
• Single 3.3V power supply  
• LVTTLinterface  
PIN CONFIGURATIONS  
54-Pin TSOP (Type II)  
• Programmable burst length  
– (1, 2, 4, 8, full page)  
VCC  
I/O0  
VCCQ  
I/O1  
I/O2  
GNDQ  
I/O3  
I/O4  
VCCQ  
I/O5  
I/O6  
GNDQ  
I/O7  
VCC  
LDQM  
WE  
1
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
GND  
I/O15  
GNDQ  
I/O14  
I/O13  
VCCQ  
I/O12  
I/O11  
GNDQ  
I/O10  
I/O9  
VCCQ  
I/O8  
GND  
NC  
• Programmableburstsequence:  
Sequential/Interleave  
2
3
4
• Self refresh modes  
5
6
• 4096 refresh cycles every 64 ms  
• Random column address every clock cycle  
• Programmable CAS latency (2, 3 clocks)  
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
• Burst read/write and burst read/single write  
operationscapability  
• Burst termination by burst stop and precharge  
command  
UDQM  
CLK  
CKE  
NC  
CAS  
RAS  
CS  
• Byte controlled by LDQM and UDQM  
• Industrialtemperatureavailability  
• Package: 400-mil 54-pin TSOP II  
BA0  
BA1  
A10  
A11  
A9  
A8  
A0  
A7  
A1  
A6  
A2  
A5  
A3  
A4  
VCC  
GND  
PIN DESCRIPTIONS  
A0-A11  
BA0, BA1  
I/O0 to I/O15  
CLK  
Address Input  
WE  
Write Enable  
Bank Select Address  
Data I/O  
LDQM  
UDQM  
Vcc  
Lower Bye, Input/Output Mask  
Upper Bye, Input/Output Mask  
Power  
System Clock Input  
Clock Enable  
CKE  
GND  
VccQ  
GNDQ  
NC  
Ground  
CS  
Chip Select  
Power Supply for I/O Pin  
Ground for I/O Pin  
No Connection  
RAS  
Row Address Strobe Command  
Column Address Strobe Command  
CAS  
This document contains PRELIMINARY SPECIFICATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best  
possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
PRELIMINARYSPECIFICATION Rev. 00A  
1
12/01/01  

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