IS42/45R86400D/16320D/32160D
IS42/45S86400D/16320D/32160D
16Mx32, 32Mx16, 64Mx8
SEPTEMBER 2012
512Mb SDRAM
DEVICE OVERVIEW
ISSI's 512Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
Theꢀ512MbꢀSDRAMꢀisꢀorganizedꢀasꢀfollows.ꢀ
FEATURES
•ꢀ Clock frequency: 200, 166, 143 MHz
•ꢀ Fullyꢀsynchronous;ꢀallꢀsignalsꢀreferencedꢀtoꢀaꢀ
positive clock edge
PACKAGE INFORMATION
IS42/45S32160D IS42/45S16320D IS42/45S86400D
•ꢀ Internalꢀbankꢀforꢀhidingꢀrowꢀaccess/precharge
•ꢀ Powerꢀsupply:ꢀVdd/Vddq = 2.3V-3.6V
ꢀ IS42/45SxxxxxDꢀ-ꢀVdd/Vddq = 3.3Vꢀ
ꢀ IS42/45RxxxxxDꢀ-ꢀVdd/Vddq = 2.5
•ꢀ LVTTLꢀinterface
IS42/45R32160D IS42/45R16320D IS42/45R86400D
4M x 32 x 4
banks
8M x 16 x 4
banks
16M x 8 x 4
banks
90-ballꢀTF-BGA
54-pinꢀTSOP-II
54-ballꢀTF-BGA
54-pinꢀTSOP-II
•ꢀ Programmableꢀburstꢀlengthꢀ
– (1, 2, 4, 8, full page)
KEY TIMING PARAMETERS
•ꢀ Programmableꢀburstꢀsequence:ꢀ
Sequential/Interleave
Parameter
-5
-6
-7
Unit
•ꢀ AutoꢀRefreshꢀ(CBR)
•ꢀ SelfꢀRefresh
•ꢀ 8Kꢀrefreshꢀcyclesꢀeveryꢀ64ꢀms
•ꢀ Randomꢀcolumnꢀaddressꢀeveryꢀclockꢀcycle
•ꢀ ProgrammableꢀCAS latency (2, 3 clocks)
ClkꢀCycleꢀTimeꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀꢀ
5ꢀ
10ꢀ
ꢀ
6ꢀ
10ꢀ
ꢀ
7ꢀ
7.5ꢀ
ꢀ
nsꢀ
ns
ClkꢀFrequencyꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀꢀ
200ꢀ
100ꢀ
ꢀ
ꢀ
ꢀ
167ꢀ
100ꢀ
143ꢀ
133ꢀ
Mhzꢀ
Mhz
AccessꢀTimeꢀꢀfromꢀClockꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ Burstꢀread/writeꢀandꢀburstꢀread/singleꢀwriteꢀ
5.0ꢀ
6ꢀ
5.4ꢀ
6ꢀ
5.4ꢀ
5.4
nsꢀ
ns
operations capability
•ꢀ Burstꢀterminationꢀbyꢀburstꢀstopꢀandꢀprechargeꢀ
command
ADDRESS TABLE
•ꢀ Packages:ꢀ
x8/x16:ꢀ54-pinꢀTSOP-II,ꢀ54-ballꢀTF-BGAꢀ(x16ꢀonly)
x32:ꢀ90-ballꢀTF-BGA
Parameter
16M x 32
32M x 16
64M x 8
16M x 8 x 4
banks
Configuration 4M x 32 x 4
8M x 16 x 4
banks
banks
BankꢀAddressꢀ BA0,ꢀBA1
Pins
•ꢀ TemperatureꢀRange:
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
Automotive, A1 (-40oC to +85oC)
BA0,ꢀBA1
BA0,ꢀBA1
Autoprecharge A10/AP
Pins
A10/AP
A10/AP
Automotive, A2 (-40oC to +105oC)
Row Address 8K(A0ꢀ–ꢀA12) 8K(A0ꢀ–ꢀA12) 8K(A0ꢀ–ꢀA12)
Column
512(A0 – A8) 1K(A0ꢀ–ꢀA9)
2K(A0ꢀ–ꢀA9,ꢀ
Address
A11)
Refresh Count
Com./Ind./A1 8Kꢀ/ꢀ64ms
A2 8Kꢀ/ꢀ16ms
8Kꢀ/ꢀ64ms
8Kꢀ/ꢀ16ms
8Kꢀ/ꢀ64ms
8Kꢀ/ꢀ16ms
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain
the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such ap-
plications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. A
08/29/2012
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