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ICS93716GLF-T PDF预览

ICS93716GLF-T

更新时间: 2024-11-06 15:34:39
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
12页 117K
描述
Clock Driver

ICS93716GLF-T 技术参数

是否Rohs认证: 符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.84
Base Number Matches:1

ICS93716GLF-T 数据手册

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ICS93716  
Integrated  
Circuit  
Systems,Inc.  
Low Cost DDR Phase Lock Loop Clock Driver  
RecommendedApplication:  
DDR Clock Driver  
Pin Configuration  
CLKC0  
CLKT0  
VDD  
CLKT1  
CLKC1  
GND  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
GND  
CLKC5  
CLKT5  
CLKC4  
CLKT4  
VDD  
SDATA  
FBINC  
FBINT  
FB_OUTT  
FB_OUTC  
CLKT3  
CLKC3  
GND  
ProductDescription/Features:  
Low skew, low jitter PLL clock driver  
I2C for functional and output control  
Feedback pins for input to output synchronization  
Spread Spectrum tolerant inputs  
SCLK  
CLK_INT  
CLK_INC  
VDDA  
GND  
VDD  
CLKT2  
CLKC2  
SwitchingCharacteristics:  
PEAK - PEAK jitter (66MHz): <120ps  
PEAK - PEAK jitter (>100MHz): <75ps  
CYCLE - CYCLE jitter (>100MHz):<65ps  
OUTPUT - OUTPUT skew: <100ps  
28-Pin SSOP and TSSOP  
Output Rise and Fall Time: 650ps - 950ps  
Functionality  
INPUTS  
OUTPUTS  
PLL State  
AVDD CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC  
2.5V  
(nom)  
L
H
L
L
H
Z
H
L
L
H
Z
H
L
on  
on  
off  
2.5V  
(nom)  
H
2.5V  
(nom)  
<20MHz  
Z
Z
GND  
GND  
L
H
L
L
H
L
L
H
L
Bypassed/off  
Bypassed/off  
Block Diagram  
H
H
H
FB_OUTT  
FB_OUTC  
Control  
SCLK  
CLKT0  
CLKC0  
Logic  
SDATA  
CLKT1  
CLKC1  
CLKT2  
CLKC2  
CLKT3  
CLKC3  
FB_INT  
FB_INC  
PLL  
CLK_INC  
CLK_INT  
CLKT4  
CLKC4  
CLKT5  
CLKC5  
0420F—04/06/05  

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