Datasheet > ICS93722

ICS93722

更新时间： 2024-11-05 22:55:27

品牌	Logo	应用领域
矽成 - ICSI		双倍数据速率
页数	文件大小	规格书
6页	56K
描述
Low Cost DDR Phase Lock Loop Zero Delay Buffer

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中文翻译

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数据手册

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ICS93722 数据手册

ICS93722

Integrated

Circuit

Systems, Inc.

Low Cost DDR Phase Lock Loop Zero Delay Buffer

Recommended Application:

Pin Configuration

DDR Zero Delay Clock Buffer

CLKC0

CLKT0

VDD

CLKT1

CLKC1

GND

SCLK

CLK_INT

N/C

VDDA

GND

VDD

CLKT2

CLKC2

GND

CLKC5

CLKT5

CLKC4

CLKT4

VDD

SDATA

N/C

FB_INT

FB_OUTT

N/C

Product Description/Features:

•

Low skew, low jitter PLL clock driver

I²C for functional and output control

Feedback pins for input to output synchronization

•

Spread Spectrum tolerant inputs

3.3V tolerant CLK_INT input

SwitchingCharacteristics:

CLKT3

CLKC3

GND

•

PEAK - PEAK jitter (66MHz): <120ps

PEAK - PEAK jitter (>100MHz): <75ps

CYCLE - CYCLE jitter (66MHz):<110ps

CYCLE - CYCLE jitter (>100MHz):<65ps

OUTPUT - OUTPUT skew: <100ps

Output Rise and Fall Time: 650ps - 950ps

DUTY CYCLE: 49.5% - 50.5%

28-Pin SSOP

Functionality

Block Diagram

INPUTS

OUTPUTS

PLL State

AVDD CLK_INT CLKT CLKC FB_OUTT

2.5V

FB_OUTT

off

(nom)

Control

SCLK

CLKT0

CLKC0

2.5V

(nom)

Logic

SDATA

CLKT1

CLKC1

2.5V

(nom)

<20MHz

CLKT2

CLKC2

CLKT3

CLKC3

FB_INT

PLL

CLKT4

CLKC4

CLK_INT

CLKT5

CLKC5

0539E—07/18/03

12 3 4 5 6

中文翻译

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与ICS93722相关器件

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ICS93722YFLFT	ICSI	获取价格	Low Cost DDR Phase Lock Loop Zero Delay Buffer
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ICS93725YFT	ICSI	获取价格	DDR and SDRAM Zero Delay Buffer
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ICS93727YF-T	IDT	获取价格	PLL Based Clock Driver, 10 True Output(s), 10 Inverted Output(s), PDSO48, 0.300 INCH, SSOP