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ICS93735

更新时间: 2024-09-15 22:55:27
品牌 Logo 应用领域
矽成 - ICSI 双倍数据速率时钟
页数 文件大小 规格书
7页 127K
描述
DDR Phase Lock Loop Zero Delay Clock Buffer

ICS93735 数据手册

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ICS93735  
Integrated  
Circuit  
Systems, Inc.  
DDR Phase Lock Loop Zero Delay Clock Buffer  
RecommendedApplication:  
Pin Configuration  
DDR Zero Delay Clock Buffer  
Product Description/Features:  
Low skew, low jitter PLL clock driver  
Max frequency supported = 266MHz (DDR 533)  
I2C for functional and output control  
Feedback pins for input to output synchronization  
Spread Spectrum tolerant inputs  
3.3V tolerant CLK_INT input  
Switching Characteristics:  
CYCLE - CYCLE jitter (66MHz): <120ps  
CYCLE - CYCLE jitter (>100MHz): <65ps  
CYCLE - CYCLE jitter (>200MHz): <75ps  
OUTPUT - OUTPUT skew: <100ps  
Output Rise and Fall Time: 500ps - 700ps  
DUTY CYCLE: 49.5% - 50.5%  
48-Pin SSOP  
Functionality  
INPUTS  
OUTPUTS  
PLL State  
AVDD  
2.5V (nom)  
2.5V (nom)  
2.5V (nom)  
GND  
CLK_INT  
CLKT  
L
H
CLKC  
H
L
FB_OUTT  
L
H
L
H
on  
on  
off  
< offset freq* offset freq* offset freq* offset freq*  
L
H
L
H
H
L
L
H
Bypassed/off  
Bypassed/off  
GND  
* The offset frequency is ~ 20 MHz, varying somewhat from part to part.  
Block Diagram  
FB_OUTT  
CLKT0  
CLKC0  
CLKT1  
CLKC1  
Control  
Logic  
CLKT2  
CLKC2  
SCLK  
SDATA  
CLKT3  
CLKC3  
CLKT4  
CLKC4  
CLKT5  
CLKC5  
FB_INT  
PLL  
CLKT6  
CLKC6  
CLK_INT  
CLKT7  
CLKC7  
CLKT8  
CLKC8  
CLKT9  
CLKC9  
0579E—08/06/03  

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