Datasheet > ICS93776

ICS93776

更新时间： 2024-09-15 21:53:59

品牌	Logo	应用领域
矽成 - ICSI		双倍数据速率
页数	文件大小	规格书
8页	83K
描述
Low Cost DDR Phase Lock Loop Zero Delay Buffer

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中文翻译

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数据手册

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ICS93776 数据手册

ICS93776

Integrated

Circuit

Systems,Inc.

LowCostDDRPhaseLockLoopZeroDelayBuffer

Recommended Application:

DDR Zero Delay Clock Buffer

PinConfiguration

DDRC0

DDRT0

VDD

DDRT1

DDRC1

GND

SCLK

CLK_INT

CLK_INC

28 GND

27 DDRC5

26 DDRT5

25 DDRC4

24 DDRT4

23 VDD

22 SDATA

21 FB_INC

20 FB_INT

19 FB_OUTT

18 FB_OUTC

17 DDRT3

16 DDRC3

15 GND

ProductDescription/Features:

•

Low skew, low jitter PLL clock driver

Max frequency supported = 266MHz (DDR 533)

I²C for functional and output control

Feedback pins for input to output synchronization

•

Spread Spectrum tolerant inputs

3.3V tolerant CLK_INT/C input

VDDA 10

GND 11

VDD 12

DDRT2 13

DDRC2 14

Switching Characteristics:

•

CYCLE - CYCLE jitter: <100ps

OUTPUT - OUTPUT skew: <100ps

DUTY CYCLE: 48% - 52%

28-Pin 209mil SSOP

BlockDiagram

Functionality

INPUTS

OUTPUTS

PLL State

AVDD CLK_INT CLKT CLKC FB_OUTT

FB_OUTT

FB_OUTC

2.5V

Coonnttrrooll

SCLK

(nom)

DDRT0

DDRC0

Looggiicc

SDATA

2.5V

(nom)

DDRT1

DDRC1

DDRT2

DDRC2

FB_INC

FB_INT

DDRT3

DDRC3

PLLLL

DDRT4

DDRC4

CLK_INT

CLK_INC

DDRT5

DDRC5

0793A—03/08/05

ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.

ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.

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