Datasheet > ICS93725YFT

ICS93725YFT

更新时间： 2024-11-08 22:09:47

品牌	Logo	应用领域
矽成 - ICSI		逻辑集成电路光电二极管驱动动态存储器双倍数据速率
页数	文件大小	规格书
8页	67K
描述
DDR and SDRAM Zero Delay Buffer

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中文翻译

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数据手册

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ICS93725YFT 数据手册

ICS93725

Integrated

Circuit

Systems, Inc.

DDR and SDRAM Zero Delay Buffer

RecommendedApplication:

Pin Configuration

DDR & SDRAM Zero Delay Buffer for SIS 635/640/645/

650 & 735/740/746 style chipsets.

VDD3.3

SDRAM0

SDRAM1

SDRAM2

SDRAM3

GND

SEL_DDR*

DDRFB_IN

DDRFB_OUT

VDD2.5

DDRT5

DDRC5

DDRT4

DDRC4

GND

VDD2.5

DDRT3

DDRC3

DDRT2

DDRC2

GND

VDD2.5

DDRT1

DDRC1

DDRT0

DDRC0

GND

VDD2.5

SCLK

SDATA

ProductDescription/Features:

•

Low skew, Zero Delay Buffer

1 to 13 SDRAM PC133 clock distribution

VDD3.3

SDRAM4

SDRAM5

BUFFER_IN

SDRAM6

SDRAM7

GND

•

1 to 6 pairs of DDR clock distribution

I²C for functional and output control

Separate feedback path for both memory mode to

adjust synchronization.

VDD3.3

•

Supports up to 2 DDR DIMMs or 3 SDRAM DIMMs

Frequency support for up to 200MHz

Individual I²C clock stop for power mananagement

CMOS level control signal input

SDRAM8

SDRAM9

SDRAM10

SDRAM11

GND

VDD3.3

SDRAM12

SDFB_OUT

SDFB_IN

GND

SwitchingCharacteristics:

•

OUTPUT - OUTPUT skew: <100ps

•

Output Rise and Fall Time for DDR outputs: 550ps -

1150ps

48-Pin SSOP

•

DUTY CYCLE: 47% - 53%

*Internal Pull-up Resistor of 120K to VDD

Block Diagram

Functionality

VDD

3.3_2.5

MODE

PIN 48

SDRAMFB_OUT

DDRFB_OUT

BUFFER_IN

SDRAMFB_IN

DDRFB_IN

PLL1

DDR

Mode

SEL_DDR=1

SEL_DDR=0

2.5V

SDRAM (12:0)

DDR/SD

Mode

3.3V

Control

Logic

DDRT (5:0)

DDRCC (5:0)

SEL_DDR*

SDATA

SCLK

Config.

Reg.

0606A—08/01/03

12 3 4 5 6 7 8

中文翻译

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与ICS93725YFT相关器件

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ICS93727F-T	IDT	获取价格	Clock Driver
ICS93727YFLF-T	IDT	获取价格	PLL Based Clock Driver, 10 True Output(s), 10 Inverted Output(s), PDSO48, 0.300 INCH, SSOP
ICS93727YF-T	IDT	获取价格	PLL Based Clock Driver, 10 True Output(s), 10 Inverted Output(s), PDSO48, 0.300 INCH, SSOP
ICS93732	ICSI	获取价格	Low Cost DDR Phase Lock Loop Zero Delay Buffer
ICS93732AF	IDT	获取价格	PLL Based Clock Driver, 93732 Series, 6 True Output(s), 6 Inverted Output(s), PDSO28, 0.20
ICS93732AFLF	IDT	获取价格	PLL Based Clock Driver, 93732 Series, 6 True Output(s), 6 Inverted Output(s), PDSO28, 0.20
ICS93732AFLFT	IDT	获取价格	PLL Based Clock Driver, 93732 Series, 6 True Output(s), 6 Inverted Output(s), PDSO28, 0.20
ICS93732AFLF-T	IDT	获取价格	93732 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28, 0.20
ICS93732AFT	IDT	获取价格	PLL Based Clock Driver, 93732 Series, 6 True Output(s), 6 Inverted Output(s), PDSO28, 0.20
ICS93732AF-T	IDT	获取价格	93732 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28, 0.20