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ICS93732FLF-T PDF预览

ICS93732FLF-T

更新时间: 2024-09-15 22:11:47
品牌 Logo 应用领域
矽成 - ICSI 双倍数据速率
页数 文件大小 规格书
8页 482K
描述
Low Cost DDR Phase Lock Loop Zero Delay Buffer

ICS93732FLF-T 数据手册

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ICS93732  
Integrated  
Circuit  
Systems,Inc.  
LowCostDDRPhaseLockLoopZeroDelayBuffer  
Recommended Application:  
DDR Zero Delay Clock Buffer  
PinConfiguration  
DDRC0  
DDRT0  
VDD  
DDRT1  
DDRC1  
GND  
SCLK  
CLK_INT  
N/C  
1
2
3
4
5
6
7
8
9
28 GND  
27 DDRC5  
26 DDRT5  
25 DDRC4  
24 DDRT4  
23 VDD  
22 SDATA  
21 N/C  
20 FB_INT  
19 FB_OUT  
18 N/C  
ProductDescription/Features:  
Low skew, low jitter PLL clock driver  
Max frequency supported = 266MHz (DDR 533)  
I2C for functional and output control  
Feedback pins for input to output synchronization  
Spread Spectrum tolerant inputs  
3.3V tolerant CLK_INT input  
VDDA 10  
GND 11  
Switching Characteristics:  
CYCLE - CYCLE jitter (66MHz): <120ps  
CYCLE - CYCLE jitter (>100MHz): <65ps  
CYCLE - CYCLE jitter (>200MHz): <75ps  
OUTPUT - OUTPUT skew: <100ps  
DUTY CYCLE: 49.5% - 50.5%  
VDD 12  
DDRT2 13  
DDRC2 14  
17 DDRT3  
16 DDRC3  
15 GND  
28-Pin 209mil SSOP  
28-Pin 173mil TSSOP  
BlockDiagram  
Functionality  
INPUTS  
OUTPUTS  
PLL State  
AVDD CLK_INT CLKT CLKC FB_OUTT  
FB_OUTT  
2.5V  
(nom)  
L
L
H
L
L
on  
on  
Control  
SCLK  
DDRT0  
DDRC0  
Logic  
SDATA  
2.5V  
(nom)  
H
H
H
DDRT1  
DDRC1  
DDRT2  
DDRC2  
DDRT3  
DDRC3  
FB_INT  
PLL  
DDRT4  
DDRC4  
CLK_INT  
DDRT5  
DDRC5  
0578H—02/19/04  

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