Datasheet > ICS93716YF-T

ICS93716YF-T

更新时间： 2024-11-05 22:21:39

品牌	Logo	应用领域
矽成 - ICSI		时钟驱动器逻辑集成电路光电二极管双倍数据速率
页数	文件大小	规格书
12页	90K
描述
Low Cost DDR Phase Lock Loop Clock Driver

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中文翻译

获取价格

数据手册

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ICS93716YF-T 数据手册

ICS93716

Integrated

Circuit

Systems,Inc.

Low Cost DDR Phase Lock Loop Clock Driver

RecommendedApplication:

Pin Configuration

DDR Clock Driver

CLKC0

CLKT0

VDD

CLKT1

CLKC1

GND

CLKC5

CLKT5

CLKC4

CLKT4

VDD

SDATA

FBINC

FBINT

FB_OUTT

FB_OUTC

CLKT3

CLKC3

GND

ProductDescription/Features:

•

Low skew, low jitter PLL clock driver

I²C for functional and output control

•

Feedback pins for input to output synchronization

Spread Spectrum tolerant inputs

SCLK

CLK_INT

CLK_INC

VDDA

GND

VDD

CLKT2

CLKC2

SwitchingCharacteristics:

•

PEAK - PEAK jitter (66MHz): <120ps

PEAK - PEAK jitter (>100MHz): <75ps

CYCLE - CYCLE jitter (>100MHz):<65ps

OUTPUT - OUTPUT skew: <100ps

28-Pin SSOP and TSSOP

Output Rise and Fall Time: 650ps - 950ps

Functionality

INPUTS

OUTPUTS

PLL State

AVDD CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC

2.5V

(nom)

off

2.5V

(nom)

2.5V

(nom)

<20MHz

GND

Bypassed/off

Block Diagram

FB_OUTT

FB_OUTC

Control

SCLK

CLKT0

CLKC0

Logic

SDATA

CLKT1

CLKC1

CLKT2

CLKC2

CLKT3

CLKC3

FB_INT

FB_INC

PLL

CLK_INC

CLK_INT

CLKT4

CLKC4

CLKT5

CLKC5

0420E—04/01/03

12 3 4 5 6 7...12

中文翻译

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