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HMP31GF7AFR4C-S5D6 PDF预览

HMP31GF7AFR4C-S5D6

更新时间: 2024-09-17 14:51:11
品牌 Logo 应用领域
海力士 - HYNIX 动态存储器双倍数据速率内存集成电路
页数 文件大小 规格书
22页 330K
描述
DDR DRAM Module, 1GX72, CMOS, HALOGEN FREE, ROHS COMPLIANT, DIMM-240

HMP31GF7AFR4C-S5D6 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:DIMM包装说明:DIMM,
针数:240Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.84Is Samacsys:N
访问模式:DUAL BANK PAGE BURST其他特性:AUTO/SELF REFRESH
JESD-30 代码:R-XSMA-N240内存密度:77309411328 bit
内存集成电路类型:DDR DRAM MODULE内存宽度:72
功能数量:1端口数量:1
端子数量:240字数:1073741824 words
字数代码:1000000000工作模式:SYNCHRONOUS
最高工作温度:95 °C最低工作温度:
组织:1GX72封装主体材料:UNSPECIFIED
封装代码:DIMM封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified自我刷新:YES
最大供电电压 (Vsup):1.575 V最小供电电压 (Vsup):1.455 V
标称供电电压 (Vsup):1.5 V表面贴装:NO
技术:CMOS温度等级:OTHER
端子形式:NO LEAD端子位置:SINGLE
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

HMP31GF7AFR4C-S5D6 数据手册

 浏览型号HMP31GF7AFR4C-S5D6的Datasheet PDF文件第2页浏览型号HMP31GF7AFR4C-S5D6的Datasheet PDF文件第3页浏览型号HMP31GF7AFR4C-S5D6的Datasheet PDF文件第4页浏览型号HMP31GF7AFR4C-S5D6的Datasheet PDF文件第5页浏览型号HMP31GF7AFR4C-S5D6的Datasheet PDF文件第6页浏览型号HMP31GF7AFR4C-S5D6的Datasheet PDF文件第7页 
240pin Fully Buffered DDR2 SDRAM DIMMs based on 2Gb A ver.  
This Hynix’s Fully Buffered DIMM is a high-bandwidth & large capacity channel solution that has a narrow  
host interface. Hynix’s FB-DIMM features novel architecture including the Advanced Memory Buffer that  
isolates the DDR2 SDRAMs from the channel. This single component located in the front side center of  
each DIMM, acts as a repeater and buffer for all signals and commands which are exchanged between the  
host controller and the DDR2 SDRAMs including data in and output. The AMB communicates with the host  
controller and adjacent DIMMs on a system board using an industry standard Differential Point to Point  
Link Interface at 1.5V power.  
The AMB also allows buffering of memory traffic to support large memory capacities. All memory control  
for the DDR2 SDRAM devices resides in the host, including memory request initiation, timing, refresh,  
scrubbing, sparing, configuration access and power management. The AMB interface is responsible for  
handling channel and memory requests to and from the local FBDIMM and for forwarding request to other  
FBDIMMs on the memory channel.  
FEATURES  
240 pin Fully Buffered ECC dual-In-Line DDR2 SDRAM Module  
JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply  
All inputs and outputs are compatible with SSTL_1.8 interface  
Built with 2Gb DDR2 SDRAMs in 60ball FBGA  
Host interface and AMB component industry standard compliant  
MBIST IBIST test functions  
8 Bank architecture  
OCD (Off-Chip Driver Impedance Adjustment)  
ODT (On-Die Termination)  
Fully differential clock operations (CK & CK)  
Programmable Burst Length 4 / 8 with both sequential and interleave mode  
Auto refresh and self refresh supported  
8192 refresh cycles / 64ms  
Serial presence detect with EEPROM  
133.35 x 30.35 mm form factor  
RoHS compliant  
Full DIMM Heat Spreader  
ORDERING INFORMATION  
# of  
DRAMs  
# of  
ranks  
Part Name  
Density Organization  
H. S type  
Materials  
Halogen  
free  
HMP31GF7AFR4C-Y5xx/Sxxx  
8GB  
1Gx72  
36  
2
FDHS**  
Note:  
*: FDHS means Full DIMM Heat Spreader.  
This document is a general product description and is subject to change without notice. Hynix Electronics does not  
assume any responsibility for use of circuits described. No patent licenses are implied.  
1
Rev 0.01 / Jan. 2009  

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