Datasheet > HMP31GP7AFR4C-S5

HMP31GP7AFR4C-S5

更新时间： 2024-09-17 05:36:19

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器双倍数据速率
页数	文件大小	规格书
18页	195K
描述
240pin Registered DDR2 SDRAM DIMMs based on 2Gb version A

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数据手册

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HMP31GP7AFR4C-S5 数据手册

240pin Registered DDR2 SDRAM DIMMs based on 2Gb version A

This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 2Gb version A DDR2

SDRAMs in Fine Ball Grid Array (FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 2Gb ver-

sion A based Registered DDR2 DIMM series provide a high performance 8 byte interface in 5.25" width

form factor of industry standard. It is suitable for easy interchange and addition.

FEATURES

•

JEDEC standard Double Data Rate2 Synchro-

nous DRAMs (DDR2 SDRAMs) with 1.8V +/-

0.1V Power Supply

•

Fully differential clock operations (CK & CK)

Programmable Burst Length 4 / 8 with both

sequential and interleave mode

•

All inputs and outputs are compatible with

SSTL_1.8 interface

•

Auto refresh and self refresh supported

8192 refresh cycles / 64ms

•

8 Bank architecture

Serial presence detect with EEPROM

DDR2 SDRAM Package: 60 ball(x4/x8)

133.35 x 30.00 mm form factor

RoHS compliant

Posted CAS

Programmable CAS Latency 3, 4, 5, 6

OCD (Off-Chip Driver Impedance Adjustment)

ODT (On-Die Termination)

ORDERING INFORMATION

# of

DRAMs

# of

ranks

Parity

Support

Part Name

Density

Organization

HMP31GP7AFR4C - Y5/S5/S6

8GB

1G X 72

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.1 / Jan. 2009

12 3 4 5 6 7...18

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