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HMP351U7AFR8C-S5 PDF预览

HMP351U7AFR8C-S5

更新时间: 2024-11-07 05:36:19
品牌 Logo 应用领域
海力士 - HYNIX 存储内存集成电路动态存储器双倍数据速率时钟
页数 文件大小 规格书
20页 217K
描述
240pin DDR2 SDRAM Unbuffered DIMMs based on 2Gb A version

HMP351U7AFR8C-S5 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:DIMM
包装说明:DIMM, DIMM240,40针数:240
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.36风险等级:5.84
Is Samacsys:N访问模式:DUAL BANK PAGE BURST
最长访问时间:0.4 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):400 MHzI/O 类型:COMMON
JESD-30 代码:R-XDMA-N240内存密度:38654705664 bit
内存集成电路类型:DDR DRAM MODULE内存宽度:72
功能数量:1端口数量:1
端子数量:240字数:536870912 words
字数代码:512000000工作模式:SYNCHRONOUS
最高工作温度:55 °C最低工作温度:
组织:512MX72输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:DIMM
封装等效代码:DIMM240,40封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY峰值回流温度(摄氏度):260
电源:1.8 V认证状态:Not Qualified
刷新周期:8192自我刷新:YES
子类别:Other Memory ICs最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:1 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20Base Number Matches:1

HMP351U7AFR8C-S5 数据手册

 浏览型号HMP351U7AFR8C-S5的Datasheet PDF文件第2页浏览型号HMP351U7AFR8C-S5的Datasheet PDF文件第3页浏览型号HMP351U7AFR8C-S5的Datasheet PDF文件第4页浏览型号HMP351U7AFR8C-S5的Datasheet PDF文件第5页浏览型号HMP351U7AFR8C-S5的Datasheet PDF文件第6页浏览型号HMP351U7AFR8C-S5的Datasheet PDF文件第7页 
240pin DDR2 SDRAM Unbuffered DIMMs based on 2Gb A version  
This Hynix unbuffered Dual In-Line Memory Module (DIMM) series consists of 2Gb A version DDR2  
SDRAMs in Fine Ball Grid Array (FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 2Gb  
version A based DDR2 Unbuffered DIMM series provide a high performance 8 byte interface in 133.35mm  
width form factor of industry standard. It is suitable for easy interchange and addition.  
FEATURES  
JEDEC standard Double Data Rate2  
Synchronous DRAMs (DDR2 SDRAMs) with  
1.8V +/- 0.1V Power Supply  
Fully differential clock operations (CK & CK)  
Programmable Burst Length 4 / 8 with both  
sequential and interleave mode  
All inputs and outputs are compatible with  
SSTL_1.8 interface  
Auto refresh and self refresh supported  
8192 refresh cycles / 64ms  
8 Bank architecture  
Serial presence detect with EEPROM  
Posted CAS  
DDR2 SDRAM Package:  
60ball FBGA(256Mx8)  
Programmable CAS Latency 3,4,5, 6  
OCD (Off-Chip Driver Impedance Adjustment)  
ODT (On-Die Termination)  
133.35 x 30.00 mm form factor  
RoHS compliant  
ORDERING INFORMATION  
# of  
# of  
Part Name  
Density  
Org.  
DRAM  
s
Materials  
ECC  
ranks  
HMP351U6AFR8C - Y5/S5/S6  
HMP351U7AFR8C - Y5/S5/S6  
4GB  
4GB  
512Mx64  
512Mx72  
16  
18  
2
2
Halogen-free None  
Halogen-free ECC  
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev. 0.1 / Mar 2009  
1

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