Datasheet > HMP351U6AFR8C-S6

HMP351U6AFR8C-S6

更新时间： 2024-11-07 05:36:19

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器双倍数据速率
页数	文件大小	规格书
20页	217K
描述
240pin DDR2 SDRAM Unbuffered DIMMs based on 2Gb A version

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中文翻译

获取价格

数据手册

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HMP351U6AFR8C-S6 数据手册

240pin DDR2 SDRAM Unbuffered DIMMs based on 2Gb A version

This Hynix unbuffered Dual In-Line Memory Module (DIMM) series consists of 2Gb A version DDR2

SDRAMs in Fine Ball Grid Array (FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 2Gb

version A based DDR2 Unbuffered DIMM series provide a high performance 8 byte interface in 133.35mm

width form factor of industry standard. It is suitable for easy interchange and addition.

FEATURES

•

JEDEC standard Double Data Rate2

Synchronous DRAMs (DDR2 SDRAMs) with

1.8V +/- 0.1V Power Supply

•

Fully differential clock operations (CK & CK)

Programmable Burst Length 4 / 8 with both

sequential and interleave mode

All inputs and outputs are compatible with

SSTL_1.8 interface

•

Auto refresh and self refresh supported

8192 refresh cycles / 64ms

•

8 Bank architecture

Serial presence detect with EEPROM

Posted CAS

DDR2 SDRAM Package:

60ball FBGA(256Mx8)

Programmable CAS Latency 3,4,5, 6

OCD (Off-Chip Driver Impedance Adjustment)

ODT (On-Die Termination)

•

133.35 x 30.00 mm form factor

RoHS compliant

ORDERING INFORMATION

# of

Part Name

Density

Org.

DRAM

Materials

ECC

ranks

HMP351U6AFR8C - Y5/S5/S6

HMP351U7AFR8C - Y5/S5/S6

4GB

512Mx64

512Mx72

Halogen-free None

Halogen-free ECC

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.1 / Mar 2009

12 3 4 5 6 7...20

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