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FDPF20N50T PDF预览

FDPF20N50T

更新时间: 2024-01-27 06:06:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 晶体晶体管功率场效应晶体管开关脉冲功率因数校正局域网
页数 文件大小 规格书
15页 676K
描述
Power Factor Correction Converter Design

FDPF20N50T 技术参数

是否无铅: 不含铅生命周期:Active
包装说明:FLANGE MOUNT, R-PSFM-T3Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8541.29.00.95
风险等级:0.96雪崩能效等级(Eas):1110 mJ
外壳连接:ISOLATED配置:SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压:500 V最大漏极电流 (Abs) (ID):20 A
最大漏极电流 (ID):20 A最大漏源导通电阻:0.23 Ω
FET 技术:METAL-OXIDE SEMICONDUCTORJEDEC-95代码:TO-220AB
JESD-30 代码:R-PSFM-T3JESD-609代码:e3
元件数量:1端子数量:3
工作模式:ENHANCEMENT MODE最高工作温度:150 °C
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:FLANGE MOUNT峰值回流温度(摄氏度):NOT SPECIFIED
极性/信道类型:N-CHANNEL最大功率耗散 (Abs):38.5 W
最大脉冲漏极电流 (IDM):80 A认证状态:Not Qualified
子类别:FET General Purpose Power表面贴装:NO
端子面层:Tin (Sn)端子形式:THROUGH-HOLE
端子位置:SINGLE处于峰值回流温度下的最长时间:NOT SPECIFIED
晶体管应用:SWITCHING晶体管元件材料:SILICON
Base Number Matches:1

FDPF20N50T 数据手册

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www.fairchildsemi.com  
AN-6982  
Power Factor Correction Converter Design with FAN6982  
Introduction  
The FAN6982 is a 14-pin, Continuous Conduction Mode  
(CCM) Power Factor Correction (PFC) controller IC, that  
employs leading-edge modulation for average current  
control and has a number of advanced features for better  
performance and reliability. The variable output voltage  
function (range function) reduces PFC output voltage at  
light-load and low-line conditions to improve light-load  
efficiency, but can be also easily disabled using EN pin.  
The RDY signal can be used for power-on sequence  
control of the downstream DC/DC converter. A TriFault  
Detect™ function helps reduce external components and  
provides full protection for feedback loops such as open,  
short, and over voltage. FAN6982 also includes PFC soft-  
start, peak current limiting, line feed-forward, and input  
voltage brownout protection.  
This application note describes the theory of operation and  
step-by-step design considerations for a power factor  
correction power supply using the FAN6982 controller. A  
typical application circuit is shown in Figure 1, where the  
supply voltage, VDD, is supplied from a standby auxiliary  
power supply and the supply voltage for the downstream  
converter is controlled by the RDY pin.  
LBOOST  
DBOOST  
VBOUT  
F1  
AC Input  
VOUT  
CIF2  
Q1  
RDRV  
CBOOST  
CIF1  
Downstream  
DC/DC Converter  
RPL  
RCS  
D1 D2  
PWM Controller  
vCC  
RLF  
CIC2  
CIC1  
RFB1  
RRMS1  
RRMS2  
RRMS3  
RIAC  
RIC  
CRMS1  
IEA  
VEA  
FBPFC  
VREF  
VDD  
IAC  
RVC  
ISENSE  
VRMS  
RDY  
CVC2  
OPFC  
PGND  
SGND  
CRMS2  
CLF  
EN  
RFB2  
CFB CVC1  
CDD  
RT/CT  
FAN6982  
Rreg1  
Q2  
REN  
RT  
CREF  
CT  
Rreg2  
Range Enabled/Disabled  
EN = VVREF : Enabled  
VEN = GND : Disabled  
V
Rreg3  
CRDY  
From Standby Auxiliary Power Supply  
Figure 1. Typical FAN6982 Application Circuit  
© 2010 Fairchild Semiconductor Corporation  
Rev. 1.0.0 • 6/8/10  
www.fairchildsemi.com  

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