FDC6320

更新时间： 2024-11-05 22:49:03

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		/
页数	文件大小	规格书
7页	103K
描述
Dual N & P Channel , Digital FET

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FDC6320 数据手册

October 1997

FDC6320C

Dual N & P Channel , Digital FET

General Description

Features

N-Ch 25 V, 0.22 A, R_DS(ON)= 5 W @ V_GS= 2.7 V.

These dual N & P Channel logic level enhancement mode field

effec transistors are produced using Fairchild's proprietary,

high cell density, DMOS technology. This very high density

process is especially tailored to minimize on-state resistance.

The device is an improved design especially for low voltage

applications as a replacement for bipolar digital transistors in

load switching applications. Since bias resistors are not

required, this dual digital FET can replace several digital

transistors with difference bias resistors.

P-Ch 25 V, -0.12 A, R_DS(ON)= 13 W @ V_GS= -2.7 V.

Very low level gate drive requirements allowing direct

operation in 3 V circuits. V_GS(th)< 1.5 V.

Gate-Source Zener for ESD ruggedness.

>6kV Human Body Model

Replace NPN & PNP digital transistors.

SuperSOT^TM-6

SuperSOT^TM-8

SOT-23

SOIC-16

SO-8

SOT-223

Absolute Maximum Ratings T_A= 25^oC unless other wise noted

Symbol Parameter

N-Channel

P-Channel

Units

V_DSS, V_CCDrain-Source Voltage, Power Supply Voltage

-25

-8

Gate-Source Voltage,

Drain/Output Current

V_GSS, V_IN

I_D, I_O

- Continuous

- Pulsed

0.22

0.5

-0.12

-0.5

Maximum Power Dissipation

(Note 1a)

(Note 1b)

0.9

P_D

0.7

Operating and Storage Tempature Ranger

-55 to 150

°C

T_J,T_STG

ESD

Electrostatic Discharge Rating MIL-STD-883D

Human Body Model (100pf / 1500 Ohm)

THERMAL CHARACTERISTICS

R_qJA

R_q_J_C

Thermal Resistance, Junction-to-Ambient

Thermal Resistance, Junction-to-Case

(Note 1a)

(Note 1)

140

°C/W

FDC6320C.Rev C

12 3 4 5 6 7

中文翻译

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与FDC6320相关器件

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FDC6321C	FAIRCHILD	获取价格	Dual N & P Channel , Digital FET
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