Datasheet > CY7C1303V25

CY7C1303V25

更新时间： 2024-09-12 23:45:23

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
28页	231K
描述
Memory

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中文翻译

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数据手册

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CY7C1303V25 数据手册

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CY7C1303V25

CY7C1306V25

Preliminary

18 Mb Burst of 2 Pipelined SRAM with QDR Architecture

Features

Functional Description

• Separate Independent Read and Write Data Ports

— Supports concurrent transactions

• 167 MHz Clock for High Bandwidth

— 2.5 ns Clock-to-Valid access time

• 2-Word Burst on all accesses

• DoubleDataRate(DDR)interfacesonbothRead&Write

Ports (data transferred at 333 MHz) @167 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) accounts for clock skew

and flight time mis-matches

• Single multiplexed address input bus latches address

inputs for both READ and WRITE ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• 2.5V core power supply with HSTL Inputs and Outputs

The CY7C1303V25 and CY7C1306V25 are 2.5V Synchro-

nous Pipelined SRAMs equipped with QDR architecture. QDR

architecture consists of two separate ports to access the mem-

ory array. The Read port has dedicated Data Outputs to sup-

port Read operations and the Write Port has dedicated Data

inputs to support Write operations. Access to each port is ac-

complished through a common address bus. The Read ad-

dress is latched on the rising edge of the K clock and the Write

address is latched on the rising edge of K clock. QDR has

separate data inputs and data outputs to completely eliminate

the need to “turn-around” the data bus required with common

I/O devices. Accesses to the CY7C1303V25/CY7C1306V25

Read and Write ports are completely independent of one an-

other. All accesses are initiated synchronously on the rising

edge of the positive input clock (K). In order to maximize data

throughput, both Read and Write ports are equipped with Dou-

ble Data Rate (DDR) interfaces. Therefore, data can be trans-

ferred into the device on every rising edge of both input clocks

(K and K) and out of the device on every rising edge of the

output clock (C and C) thereby maximizing performance while

simplifying system design. Each address location is associat-

ed with two 18-bit words (CY7C1303V25) or two 36-bit words

(CY7C1306V25) that burst sequentially into or out of the de-

vice.

• 13x15 mm 1.0 mm pitch fBGA package, 165 ball

(11x15 matrix) Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–1.9V)

• JTAG Interface

• Variable Impedance HSTL

Configurations

CY7C1303V25 – 1 Mb x 18

CY7C1306V25 – 512K x 36

Depth expansion is accomplished with a Port Select input for

each port. Each Port Selects allow each port to operate inde-

pendently.

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C input clocks. Writes are con-

ducted with on-chip synchronous self-timed write circuitry.

Logic Block Diagram (CY7C1303V25)

D_[17:0]

Write

Data Reg

Address

(18:0)

Address

A_(18:0)

512Kx18 512Kx18

Memory Memory

Array

CLK

Gen.

RPS

Control

Logic

Read Data Reg.

Vref

Reg.

Control

Logic

WPS

BWS₀

Q_[17:0]

BWS₁

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05100 Rev. *A

Revised December 11, 2002

12 3 4 5 6 7...28

中文翻译

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与CY7C1303V25相关器件

型号	品牌	获取价格	描述	数据表
CY7C1303V25-100BZC	CYPRESS	获取价格	QDR SRAM, 1MX18, 3ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
CY7C1303V25-133BZC	CYPRESS	获取价格	QDR SRAM, 1MX18, 3ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
CY7C1303V25-167BZCT	CYPRESS	获取价格	Standard SRAM, 1MX18, 2.5ns, CMOS, PBGA165
CY7C1303V25-200BZC	CYPRESS	获取价格	QDR SRAM, 1MX18, 2.3ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, FBGA-165
CY7C130-45DC	ETC	获取价格	x8 Dual-Port SRAM
CY7C130-45DI	ETC	获取价格	x8 Dual-Port SRAM
CY7C130-45DMB	CYPRESS	获取价格	1K x 8 Dual-Port Static Ram
CY7C130-45FMB	CYPRESS	获取价格	Multi-Port SRAM, 1KX8, 45ns, CMOS, CQFP48, CERAMIC, QFP-48
CY7C130-45LC	CYPRESS	获取价格	Multi-Port SRAM, 1KX8, 45ns, CMOS, CQCC48, CERAMIC, LCC-48
CY7C130-45LMB	CYPRESS	获取价格	Multi-Port SRAM, 1KX8, 45ns, CMOS, CQCC48, CERAMIC, LCC-48

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