Datasheet > CY7C1304DV25-167BZC

CY7C1304DV25-167BZC

更新时间： 2024-11-05 05:09:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
18页	421K
描述
9-Mbit Burst of 4 Pipelined SRAM with QDR⑩ Architecture

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CY7C1304DV25

9-Mbit Burst of 4 Pipelined SRAM with

QDR™ Architecture

Features

Functional Description

• Separate independent Read and Write data ports

— Supports concurrent transactions

The CY7C1304DV25 is a 2.5V Synchronous Pipelined SRAM

equipped with QDR™ architecture. QDR architecture consists

of two separate ports to access the memory array. The Read

port has dedicated Data Outputs to support Read operations

and the Write port has dedicated Data Inputs to support Write

operations. QDR architecture has separate data inputs and

data outputs to completely eliminate the need to “turn-around”

the data bus required with common I/O devices. Access to

each port is accomplished through a common address bus.

Addresses for Read and Write addresses are latched on

alternate rising edges of the input (K) clock. Accesses to the

device’s Read and Write ports are completely independent of

one another. In order to maximize data throughput, both Read

and Write ports are equipped with Double Data Rate (DDR)

interfaces. Each address location is associated with four 18-bit

words. Since data can be transferred into and out of the device

on every rising edge of both input clock (K/K and C/C) memory

bandwidth is maximized while simplifying system design by

eliminating bus “turn-arounds.”

• 167-MHz Clock for high bandwidth

— 2.5 ns Clock-to-Valid access time

• 4-Word Burst for reducing the address bus frequency

• Double Data Rate (DDR) interfaces on both Read and

Write Ports (data transferred at 333 MHz) @167 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two input clocks for output data (C and C) to minimize

clock-skew and flight-time mismatches.

• Single multiplexed address input bus latches address

inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• 2.5V core power supply with HSTL Inputs and Outputs

• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)

• Variable drive HSTL output buffers

Depth expansion is accomplished with Port Selects for each

port. Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

• Expanded HSTL output voltage (1.4V–1.9V)

• JTAG 1149.1 compatible test access port

Configurations

CY7C1304DV25 – 512K x 18

Logic Block Diagram (CY7C1304DV25)

[17:0]

Write Write Write Write

Reg

Reg Reg

Reg

Address

(16:0)

CLK

Gen.

RPS

Control

Logic

Read Data Reg.

Vref

Reg.

WPS

BWS

Control

Logic

[0:1]

[17:0]

Cypress Semiconductor Corporation

Document #: 38-05628 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 23, 2006

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与CY7C1304DV25-167BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1304DV25-167BZI	CYPRESS	获取价格	9-Mbit Burst of 4 Pipelined SRAM with QDR⑩ Ar
CY7C1304DV25-167BZXC	CYPRESS	获取价格	9-Mbit Burst of 4 Pipelined SRAM with QDR⑩ Ar
CY7C1304DV25-167BZXI	CYPRESS	获取价格	9-Mbit Burst of 4 Pipelined SRAM with QDR⑩ Ar
CY7C1304V25	ETC	获取价格	Memory
CY7C1304V25-100BZC	CYPRESS	获取价格	QDR SRAM, 128KX72, 3ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, 1 MM PITCH, FBGA-165
CY7C1304V25-133BZC	CYPRESS	获取价格	QDR SRAM, 128KX72, 3ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, 1 MM PITCH, FBGA-165
CY7C1304V25-167BZC	CYPRESS	获取价格	QDR SRAM, 128KX72, 2.5ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, 1 MM PITCH, FBGA-165
CY7C130-55DC	ETC	获取价格	x8 Dual-Port SRAM
CY7C130-55DI	CYPRESS	获取价格	Multi-Port SRAM, 1KX8, 55ns, CMOS, CDIP48, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-48
CY7C130-55DMB	CYPRESS	获取价格	1K x 8 Dual-Port Static Ram

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