Datasheet > 存储 > SRAM> CY7C1305AV18-167BZC

CY7C1305AV18-167BZC

更新时间： 2024-11-06 05:09:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
20页	483K
描述
18-Mb Burst of 4 Pipelined SRAM with QDR⑩ Architecture

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技术参数
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CY7C1305AV18-167BZC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.92
Is Samacsys：	N	最长访问时间：	2.5 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	167 MHz
I/O 类型：	SEPARATE	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e0	长度：	15 mm
内存密度：	18874368 bit	内存集成电路类型：	QDR SRAM
内存宽度：	18	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	1048576 words	字数代码：	1000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	1MX18
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	220
电源：	1.5/1.8,1.8 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大待机电流：	0.42 A
最小待机电流：	1.7 V	子类别：	SRAMs
最大压摆率：	0.65 mA	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	13 mm	Base Number Matches：	1

CY7C1305AV18-167BZC 数据手册

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CY7C1305AV18

CY7C1307AV18

PRELIMINARY

18-MbBurstof4PipelinedSRAMwithQDR™Architecture

Features

Functional Description

• Separate independent Read and Write data ports

— Supports concurrent transactions

• 167 MHz Clock for high bandwidth

— 2.5 ns Clock-to-Valid access time

• 4-Word Burst for reducing the address bus frequency

The CY7C1305AV18/CY7C1307AV18 are 1.8V Synchronous

Pipelined SRAMs equipped with QDR™ architecture. QDR

architecture consists of two separate ports to access the

memory array. The Read port has dedicated Data Outputs to

support Read operations and the Write Port has dedicated

Data Inputs to support Write operations. QDR architecture has

separate data inputs and data outputs to completely eliminate

the need to “turn-around” the data bus required with common

I/O devices. Access to each port is accomplished through a

common address bus. Addresses for Read and Write

addresses are latched on alternate rising edges of the input

(K) clock. Accesses to the device’s Read and Write ports are

completely independent of one another. In order to maximize

data throughput, both Read and Write ports are equipped with

Double Data Rate (DDR) interfaces. Each address location is

associated with four 18-bit words (CY7C1305AV18) and four

36-bit words (CY7C1307AV18) that burst sequentially into or

out of the device. Since data can be transferred into and out

of the device on every rising edge of both input clocks (K/K and

C/C) memory bandwidth is maximized while simplifying

system design by eliminating bus “turn-arounds.”

• DoubleDataRate(DDR)interfacesonbothRead&Write

Ports (data transferred at 333 MHz) @167 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) accounts for clock skew

and flight time mismatching

• Single multiplexed address input bus latches address

inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• 1.8V core power supply with HSTL Inputs and Outputs

• 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball

Depth expansion is accomplished with Port Selects for each

(11x15 matrix)

port. Port selects allow each port to operate independently.

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–1.9V)

• JTAG Interface

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

Configurations

CY7C1305AV18 – 1M x 18

CY7C1307AV18 – 512K x 36

Logic Block Diagram (CY7C1305AV18)

D_[17:0]

Write Write Write Write

Reg Reg Reg

Reg

Address

A_(17:0)

Address

A_(17:0)

CLK

RPS

Control

Logic

Gen.

Read Data Reg.

Vref

WPS

BWS_[0:1]

Reg.

Control

Logic

Q_[17:0]

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05495 Rev. *A

Revised June 1, 2004

12 3 4 5 6 7...20

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与CY7C1305AV18-167BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1305AV25	CYPRESS	获取价格	18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
CY7C1305AV25-100	CYPRESS	获取价格	18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
CY7C1305AV25-100BZC	CYPRESS	获取价格	18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
CY7C1305AV25-133	CYPRESS	获取价格	18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
CY7C1305AV25-133BZC	CYPRESS	获取价格	18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
CY7C1305AV25-167	CYPRESS	获取价格	18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
CY7C1305AV25-167BZC	CYPRESS	获取价格	18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
CY7C1305AV25-167BZCT	CYPRESS	获取价格	QDR SRAM, 1MX18, 2.5ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165
CY7C1305BV18	CYPRESS	获取价格	RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C1305BV18-100BZC	CYPRESS	获取价格	18-Mbit Burst of 4 Pipelined SRAM with QDR⑩ A

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