Datasheet > CY7C1305V25-200BZC

CY7C1305V25-200BZC

更新时间： 2024-11-06 21:13:19

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟静态存储器内存集成电路
页数	文件大小	规格书
28页	229K
描述
QDR SRAM, 1MX18, 2.3ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, FBGA-165

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CY7C1305V25-200BZC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	13 X 15 MM, 1.40 MM HEIGHT, FBGA-165	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.92
最长访问时间：	2.3 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	200 MHz	I/O 类型：	SEPARATE
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e0
长度：	15 mm	内存密度：	18874368 bit
内存集成电路类型：	QDR SRAM	内存宽度：	18
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	1048576 words
字数代码：	1000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	1MX18	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	220	电源：	1.5/1.8,2.5 V
认证状态：	Not Qualified	座面最大高度：	1.35 mm
最大待机电流：	0.125 A	最小待机电流：	2.4 V
子类别：	SRAMs	最大压摆率：	0.5 mA
最大供电电压 (Vsup)：	2.6 V	最小供电电压 (Vsup)：	2.4 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	13 mm
Base Number Matches：	1

CY7C1305V25-200BZC 数据手册

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1305V25

CY7C1305V25

CY7C1307V25

Preliminary

18 Mb Burst of 4 Pipelined SRAM with QDR Architecture

Features

Functional Description

• Separate Independent Read and Write Data Ports

The CY7C1305V25/CY7C1307V25 are 2.5V Synchronous

Pipelined SRAMs equipped with QDR architecture. QDR ar-

chitecture consists of two separate ports to access the mem-

ory array. The Read port has dedicated Data Outputs to sup-

port Read operations and the Write Port has dedicated Data

Inputs to support Write operations. QDR architecture has sep-

arate data inputs and data outputs to completely eliminate the

need to “turn-around” the data bus required with common I/O

devices. Access to each port is accomplished through a com-

mon address bus. Addresses for Read and Write addresses

are latched on alternate rising edges of the input (K) clock.

Accesses to the device’s Read and Write ports are completely

independent of one another. In order to maximize data

throughput, both Read and Write ports are equipped with Dou-

ble Data Rate (DDR) interfaces. Each address location is as-

sociated with four 18-bit words (CY7C1305V25) and four

36-bit words (CY7C1307V25) that burst sequentially into or

out of the device. Since data can be transferred into and out

of the device on every rising edge of both input clocks (K/K and

C/C) memory bandwidth is maximized while simplifying sys-

tem design by eliminating bus “turn-arounds.”

— Supports concurrent transactions

• 167 MHz Clock for High Bandwidth

— 2.5 ns Clock-to-Valid access time

• 4-Word Burst for reducing the address bus frequency

• DoubleDataRate(DDR)interfacesonbothRead&Write

Ports (data transferred at 333 MHz) @167 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) accounts for clock skew

and flight time mis-matches

• Single multiplexed address input bus latches address

inputs for both READ and WRITE ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• 2.5V core power supply with HSTL Inputs and Outputs

• 13x15 mm 1.0 mm pitch fBGA package, 165 ball

(11x15 matrix)

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–1.9V)

• JTAG Interface

Depth expansion is accomplished with Port Selects for each

port. Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C input clocks. Writes are con-

ducted with on-chip synchronous self-timed write circuitry.

Configurations

CY7C1305V25 – 1 Mb x 18

CY7C1307V25 – 512K x 36

Logic Block Diagram (CY7C1305V25)

[17:0]

Write Write Write

Write

Reg Reg Reg Reg

Address

(17:0)

CLK

Gen.

RPS

Control

Logic

Read Data Reg.

Vref

Reg.

WPS

BWS

Control

Logic

[0:1]

[17:0]

Cypress Semiconductor Corporation

Document #: 38-05099 Rev. *A

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised December 11, 2002

12 3 4 5 6 7...28

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与CY7C1305V25-200BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1306AV18	CYPRESS	获取价格	18-Mb Burst of 2 Pipelined SRAM with QDR⑩ Arc
CY7C1306AV18-100BZC	CYPRESS	获取价格	18-Mb Burst of 2 Pipelined SRAM with QDR⑩ Arc
CY7C1306AV18-133BZC	CYPRESS	获取价格	18-Mb Burst of 2 Pipelined SRAM with QDR⑩ Arc
CY7C1306AV18-167BZC	CYPRESS	获取价格	18-Mb Burst of 2 Pipelined SRAM with QDR⑩ Arc
CY7C1306AV25	CYPRESS	获取价格	18-Mb Burst of 2 Pipelined SRAM with QDR⑩ Arc
CY7C1306AV25-100BZC	CYPRESS	获取价格	18-Mb Burst of 2 Pipelined SRAM with QDR⑩ Arc
CY7C1306AV25-133BZC	CYPRESS	获取价格	18-Mb Burst of 2 Pipelined SRAM with QDR⑩ Arc
CY7C1306AV25-167BZC	CYPRESS	获取价格	18-Mb Burst of 2 Pipelined SRAM with QDR⑩ Arc
CY7C1306BV18	CYPRESS	获取价格	RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C1306BV18-100BZC	CYPRESS	获取价格	18-Mbit Burst of 2 Pipelined SRAM with QDR⑩ A

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