Datasheet > CY7C1305BV18-167BZC

CY7C1305BV18-167BZC

更新时间： 2024-11-06 05:09:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
20页	245K
描述
18-Mbit Burst of 4 Pipelined SRAM with QDR⑩ Architecture

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CY7C1305BV18

CY7C1307BV18

PRELIMINARY

18-Mbit Burst of 4 Pipelined SRAM with

QDR™ Architecture

Features

Functional Description

• Separate independent Read and Write data ports

— Supports concurrent transactions

The CY7C1305BV18/CY7C1307BV18 are 1.8V Synchronous

Pipelined SRAMs equipped with QDR™ architecture. QDR

architecture consists of two separate ports to access the

memory array. The Read port has dedicated Data Outputs to

support Read operations and the Write Port has dedicated

Data Inputs to support Write operations. QDR architecture has

separate data inputs and data outputs to completely eliminate

the need to “turn-around” the data bus required with common

I/O devices. Access to each port is accomplished through a

common address bus. Addresses for Read and Write

addresses are latched on alternate rising edges of the input

(K) clock. Accesses to the device’s Read and Write ports are

completely independent of one another. In order to maximize

data throughput, both Read and Write ports are equipped with

Double Data Rate (DDR) interfaces. Each address location is

associated with four 18-bit words (CY7C1305BV18) and four

36-bit words (CY7C1307BV18) that burst sequentially into or

out of the device. Since data can be transferred into and out

of the device on every rising edge of both input clocks (K/K and

C/C) memory bandwidth is maximized while simplifying

system design by eliminating bus “turn-arounds.”

• 167 MHz Clock for high bandwidth

— 2.5 ns Clock-to-Valid access time

• 4-Word Burst for reducing the address bus frequency

• DoubleDataRate(DDR)interfacesonbothRead&Write

Ports (data transferred at 333 MHz) @167 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) accounts for clock skew

and flight time mismatching

• Single multiplexed address input bus latches address

inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• 1.8V core power supply with HSTL Inputs and Outputs

• 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball

(11x15 matrix)

Depth expansion is accomplished with Port Selects for each

port. Port selects allow each port to operate independently.

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–1.9V)

• JTAG Interface

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

Configurations

CY7C1305BV18 – 1M x 18

CY7C1307BV18 – 512K x 36

Cypress Semiconductor Corporation

Document #: 38-05629 Rev. **

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised July 29, 2004

12 3 4 5 6 7...20

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与CY7C1305BV18-167BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1305BV18-167BZXC	CYPRESS	获取价格	QDR SRAM, 1MX18, 2.5ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA
CY7C1305BV25	CYPRESS	获取价格	18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
CY7C1305BV25_06	CYPRESS	获取价格	18-Mbit Burst of 4 Pipelined SRAM with QDR⑩ A
CY7C1305BV25-100BZC	CYPRESS	获取价格	18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
CY7C1305BV25-133BZC	CYPRESS	获取价格	18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
CY7C1305BV25-167BZC	CYPRESS	获取价格	18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
CY7C1305BV25-167BZI	CYPRESS	获取价格	18-Mbit Burst of 4 Pipelined SRAM with QDR⑩ A
CY7C1305BV25-167BZXC	CYPRESS	获取价格	18-Mbit Burst of 4 Pipelined SRAM with QDR⑩ A
CY7C1305BV25-167BZXI	CYPRESS	获取价格	18-Mbit Burst of 4 Pipelined SRAM with QDR⑩ A
CY7C1305V25	ETC	获取价格	Memory

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