Datasheet > 存储 > SRAM> CY7C1305AV25-133

CY7C1305AV25-133

更新时间： 2024-09-16 05:09:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
21页	330K
描述
18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1305AV25-133 数据手册

CY7C1305AV25

CY7C1307AV25

PRELIMINARY

18-Mbit Burst of 4 Pipelined SRAM with

QDR™ Architecture

Features

Functional Description

• Separate independent Read and Write data ports

• Supports concurrent transactions

• 167-MHz clock for high bandwidth

• 2.5 ns Clock-to-Valid access time

• 4-Word Burst for reducing the address bus frequency

The CY7C1305AV25/CY7C1307AV25 are 2.5V Synchronous

Pipelined SRAMs equipped with QDR architecture. QDR

architecture consists of two separate ports to access the

memory array. The Read port has dedicated Data Outputs to

support Read operations and the Write Port has dedicated

Data Inputs to support Write operations. QDR architecture has

separate data inputs and data outputs to completely eliminate

the need to “turn-around” the data bus required with common

I/O devices. Access to each port is accomplished through a

common address bus. Addresses for Read and Write

addresses are latched on alternate rising edges of the input

(K) clock. Accesses to the device’s Read and Write ports are

completely independent of one another. In order to maximize

data throughput, both Read and Write ports are equipped with

Double Data Rate (DDR) interfaces. Each address location is

associated with four 18-bit words (CY7C1305AV25) and four

36-bit words (CY7C1307AV25) that burst sequentially into or

out of the device. Since data can be transferred into and out

of the device on every rising edge of both input clocks (K/K and

C/C) memory bandwidth is maximized while simplifying

system design by eliminating bus “turn-arounds.”

• Double Data Rate (DDR) interfaces on both Read and

Write Ports (data transferred at 333 MHz) @167 MHz

• Two input clocks (K and K) for precise DDR timing

• SRAM uses rising edges only

• Two output clocks (C and C) accounts for clock skew

and flight time mismatching

• Single multiplexed address input bus latches address

inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• 2.5V core power supply with HSTL Inputs and Outputs

• 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball

Depth expansion is accomplished with Port Selects for each

(11x15 matrix)

port. Port selects allow each port to operate independently.

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–1.9V)

• JTAG interface

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

Configurations

• CY7C1305AV25 – 1M x 18

• CY7C1307AV25 – 512K x 36

Logic Block Diagram (CY7C1305AV25)

D_[17:0]

Write Write Write Write

Reg Reg Reg

Reg

Address

A_[17:0]

Address

A_(17:0)

CLK

RPS

Control

Logic

Gen.

Read Data Reg.

Vref

WPS

BWS_[0:1]

Reg.

Control

Logic

Q_[17:0]

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05496 Rev. *A

Revised June 1, 2004

12 3 4 5 6 7...21

中文翻译

下载PDF

与CY7C1305AV25-133相关器件

型号	品牌	获取价格	描述	数据表
CY7C1305AV25-133BZC	CYPRESS	获取价格	18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
CY7C1305AV25-167	CYPRESS	获取价格	18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
CY7C1305AV25-167BZC	CYPRESS	获取价格	18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture
CY7C1305AV25-167BZCT	CYPRESS	获取价格	QDR SRAM, 1MX18, 2.5ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165
CY7C1305BV18	CYPRESS	获取价格	RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C1305BV18-100BZC	CYPRESS	获取价格	18-Mbit Burst of 4 Pipelined SRAM with QDR⑩ A
CY7C1305BV18-133BZC	CYPRESS	获取价格	18-Mbit Burst of 4 Pipelined SRAM with QDR⑩ A
CY7C1305BV18-167BZC	CYPRESS	获取价格	18-Mbit Burst of 4 Pipelined SRAM with QDR⑩ A
CY7C1305BV18-167BZXC	CYPRESS	获取价格	QDR SRAM, 1MX18, 2.5ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA
CY7C1305BV25	CYPRESS	获取价格	18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture

与CY7C1305AV25-133相关文章

摩尔斯微电子在美国约书亚树国家公园测试 Wi-Fi HaLow
2024-09-18

6
贸泽上架Tallysman TW5386智能GNSS天线
2024-09-18

6
SL74HC10N：高性能三输入与非门解析
2024-09-03

88
AIC1781A 电池充电控制器深度解析
2024-09-03

79

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1305AV25-133

CY7C1305AV25-133 数据手册

与CY7C1305AV25-133相关器件

与CY7C1305AV25-133相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1305AV25-133

CY7C1305AV25-133 数据手册

与CY7C1305AV25-133相关器件

与CY7C1305AV25-133相关文章

您还可以找

您在本页遇到什么问题？