Datasheet > CY7C1304V25

CY7C1304V25

更新时间： 2024-10-31 23:45:23

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
24页	408K
描述
Memory

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CY7C1304V25 数据手册

CY7C1304V25

9-Mb Pipelined SRAM with QDR™ Architecture

Features

Functional Description

• Separate independent Read and Write data ports

— Supports concurrent transactions

The CY7C1304V25 is a 2.5V Synchronous Pipelined SRAM

equipped with QDR architecture. QDR architecture consists of

two separate ports to access the memory array. The Read port

has dedicated Data Outputs to support Read operations and

the Write Port has dedicated Data Inputs to support Write op-

erations. QDR architecture has separate data inputs and data

outputs to completely eliminate the need to “turn-around” the

data bus required with common I/O devices. Access to each

port is accomplished through a common address bus. Ad-

dresses for Read and Write addresses are latched on alter-

nate rising edges of the input (K)^[1]clock. Accesses to the

CY7C1304V25 Read and Write ports are completely indepen-

dent of one another. In order to maximize data throughput,

both Read and Write ports are equipped with Double Data

Rate (DDR) interfaces. Each address location is associated

with 4 18-bit words that burst sequentially into or out of the

device. Since data can be transferred into and out of the de-

vice on every rising edge of both input clocks (K/K^[1]and C/C)

memory bandwidth is maximized while simplifying system de-

sign by eliminating bus “turn-arounds”.

• 167 MHz Clock for high bandwidth

— 2.5 ns Clock-to-Valid access time

• 4-Word burst for reducing address bus frequency

• DoubleDataRate(DDR)interfacesonbothRead&Write

Ports (data transferred at 333 MHz) @167 MHz

• Two input clocks (K and K)^[1]for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) accounts for clock skew

and flight time mis-matches

• Single multiplexed address input bus latches address

inputs for both READ and WRITE ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• 2.5VcorepowersupplywithHSTLInputsandOutputs^[1]

• 13x15 mm 1.0 mm pitch fBGA package, 165 ball (11x15

matrix)

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V-1.9V)

• JTAG Interface

Depth expansion is accomplished with Port Selects for each

port. Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled

by the K or K^[1]input clocks. Data outputs pass through output

registers controlled by the C or C input clocks. Writes are con-

ducted with on-chip synchronous self-timed write circuitry.

Logic Block Diagram

[17:0]

Write Write Write

Write

Reg Reg Reg Reg

Address

(16:0)

[1]

CLK

Gen.

RPS

Control

Logic

Read Data Reg.

Vref

Reg.

WPS

BWS

Control

Logic

[0:1]

[17:0]

Selection Guide

7C1304V25-167

7C1304V25-133

7C1304V25-100

Maximum Operating Frequency (MHz)

167

450

133

350

100

230

Maximum Operating Current (mA)

Note:

1. K and K inputs require V_IHto be greater than V_REF+ 0.5V and V_ILto be less than V_REF- 0.5. This is a subset of JEDEC standards for HSTL I/Os.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05167 Rev. *A

Revised August 15, 2002

12 3 4 5 6 7...24

中文翻译

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与CY7C1304V25相关器件

型号	品牌	获取价格	描述	数据表
CY7C1304V25-100BZC	CYPRESS	获取价格	QDR SRAM, 128KX72, 3ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, 1 MM PITCH, FBGA-165
CY7C1304V25-133BZC	CYPRESS	获取价格	QDR SRAM, 128KX72, 3ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, 1 MM PITCH, FBGA-165
CY7C1304V25-167BZC	CYPRESS	获取价格	QDR SRAM, 128KX72, 2.5ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, 1 MM PITCH, FBGA-165
CY7C130-55DC	ETC	获取价格	x8 Dual-Port SRAM
CY7C130-55DI	CYPRESS	获取价格	Multi-Port SRAM, 1KX8, 55ns, CMOS, CDIP48, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-48
CY7C130-55DMB	CYPRESS	获取价格	1K x 8 Dual-Port Static Ram
CY7C130-55FMB	CYPRESS	获取价格	Multi-Port SRAM, 1KX8, 55ns, CMOS, CQFP48, CERAMIC, QFP-48
CY7C130-55LC	ETC	获取价格	x8 Dual-Port SRAM
CY7C130-55LMB	ETC	获取价格	x8 Dual-Port SRAM
CY7C130-55PC	CYPRESS	获取价格	1K x 8 Dual-Port Static Ram

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