Datasheet > CY7C1304V25-167BZC

CY7C1304V25-167BZC

更新时间： 2024-09-15 20:11:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟静态存储器内存集成电路
页数	文件大小	规格书
24页	406K
描述
QDR SRAM, 128KX72, 2.5ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, 1 MM PITCH, FBGA-165

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CY7C1304V25-167BZC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	LBGA, BGA165,11X15,40
针数：	165	Reach Compliance Code：	not_compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.88	最长访问时间：	2.5 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	167 MHz
I/O 类型：	SEPARATE	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e0	长度：	15 mm
内存密度：	9437184 bit	内存集成电路类型：	QDR SRAM
内存宽度：	72	功能数量：	1
端口数量：	2	端子数量：	165
字数：	131072 words	字数代码：	128000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	128KX72
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	1.5/1.8,2.5 V	认证状态：	Not Qualified
座面最大高度：	1.36 mm	最大待机电流：	0.1 A
最小待机电流：	2.4 V	子类别：	SRAMs
最大压摆率：	0.45 mA	最大供电电压 (Vsup)：	2.6 V
最小供电电压 (Vsup)：	2.4 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	13 mm	Base Number Matches：	1

CY7C1304V25-167BZC 数据手册

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CY7C1304V25

9-Mb Pipelined SRAM with QDR™ Architecture

Features

Functional Description

• Separate independent Read and Write data ports

— Supports concurrent transactions

The CY7C1304V25 is a 2.5V Synchronous Pipelined SRAM

equipped with QDR architecture. QDR architecture consists of

two separate ports to access the memory array. The Read port

has dedicated Data Outputs to support Read operations and

the Write Port has dedicated Data Inputs to support Write op-

erations. QDR architecture has separate data inputs and data

outputs to completely eliminate the need to “turn-around” the

data bus required with common I/O devices. Access to each

port is accomplished through a common address bus. Ad-

dresses for Read and Write addresses are latched on alter-

nate rising edges of the input (K)^[1]clock. Accesses to the

CY7C1304V25 Read and Write ports are completely indepen-

dent of one another. In order to maximize data throughput,

both Read and Write ports are equipped with Double Data

Rate (DDR) interfaces. Each address location is associated

with 4 18-bit words that burst sequentially into or out of the

device. Since data can be transferred into and out of the de-

vice on every rising edge of both input clocks (K/K^[1]and C/C)

memory bandwidth is maximized while simplifying system de-

sign by eliminating bus “turn-arounds”.

• 167 MHz Clock for high bandwidth

— 2.5 ns Clock-to-Valid access time

• 4-Word burst for reducing address bus frequency

• DoubleDataRate(DDR)interfacesonbothRead&Write

Ports (data transferred at 333 MHz) @167 MHz

• Two input clocks (K and K)^[1]for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) accounts for clock skew

and flight time mis-matches

• Single multiplexed address input bus latches address

inputs for both READ and WRITE ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• 2.5VcorepowersupplywithHSTLInputsandOutputs^[1]

• 13x15 mm 1.0 mm pitch fBGA package, 165 ball (11x15

matrix)

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V-1.9V)

• JTAG Interface

Depth expansion is accomplished with Port Selects for each

port. Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled

by the K or K^[1]input clocks. Data outputs pass through output

registers controlled by the C or C input clocks. Writes are con-

ducted with on-chip synchronous self-timed write circuitry.

Logic Block Diagram

[17:0]

Write Write Write

Write

Reg Reg Reg Reg

Address

(16:0)

[1]

CLK

Gen.

RPS

Control

Logic

Read Data Reg.

Vref

Reg.

WPS

BWS

Control

Logic

[0:1]

[17:0]

Selection Guide

7C1304V25-167

7C1304V25-133

7C1304V25-100

Maximum Operating Frequency (MHz)

167

450

133

350

100

230

Maximum Operating Current (mA)

Note:

1. K and K inputs require V_IHto be greater than V_REF+ 0.5V and V_ILto be less than V_REF- 0.5. This is a subset of JEDEC standards for HSTL I/Os.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05167 Rev. *A

Revised August 15, 2002

12 3 4 5 6 7...24

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与CY7C1304V25-167BZC相关器件

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CY7C130-55DC	ETC	获取价格	x8 Dual-Port SRAM
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CY7C130-55FMB	CYPRESS	获取价格	Multi-Port SRAM, 1KX8, 55ns, CMOS, CQFP48, CERAMIC, QFP-48
CY7C130-55LC	ETC	获取价格	x8 Dual-Port SRAM
CY7C130-55LMB	ETC	获取价格	x8 Dual-Port SRAM
CY7C130-55PC	CYPRESS	获取价格	1K x 8 Dual-Port Static Ram
CY7C130-55PI	CYPRESS	获取价格	1K x 8 Dual-Port Static Ram
CY7C1305AV18	CYPRESS	获取价格	18-Mb Burst of 4 Pipelined SRAM with QDR⑩ Arc
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