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CY7C130-45PI PDF预览

CY7C130-45PI

更新时间： 2024-11-01 04:53:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
16页 307K
描述
1K x 8 Dual-Port Static Ram

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中文翻译

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CY7C130-45PI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：0.600 INCH, DIP-48
针数：48Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.32.00.41
风险等级：5.58最长访问时间：45 ns
其他特性：INTERRUPT FLAGI/O 类型：COMMON
JESD-30 代码：R-PDIP-T48JESD-609代码：e0
长度：61.976 mm内存密度：8192 bit
内存集成电路类型：DUAL-PORT SRAM内存宽度：8
功能数量：1端口数量：2
端子数量：48字数：1024 words
字数代码：1000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1KX8输出特性：3-STATE
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP48,.6
封装形状：RECTANGULAR封装形式：IN-LINE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V认证状态：Not Qualified
座面最大高度：5.334 mm最大待机电流：0.015 A
最小待机电流：4.5 V子类别：SRAMs
最大压摆率：0.12 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：15.24 mm

CY7C130-45PI 数据手册

 浏览型号CY7C130-45PI的Datasheet PDF文件第2页浏览型号CY7C130-45PI的Datasheet PDF文件第3页浏览型号CY7C130-45PI的Datasheet PDF文件第4页浏览型号CY7C130-45PI的Datasheet PDF文件第5页浏览型号CY7C130-45PI的Datasheet PDF文件第6页浏览型号CY7C130-45PI的Datasheet PDF文件第7页 
1CY7C140  
fax id: 5200  
CY7C130/CY7C131  
CY7C140/CY7C141  
1K x 8 Dual-Port Static Ram  
Features  
Functional Description  
• True Dual-Ported memory cells which allow simulta-  
neous reads of the same memory location  
• 1K x 8 organization  
• 0.65-micron CMOS for optimum speed/power  
• High-speed access: 15 ns  
The CY7C130/CY7C131/CY7C140 and CY7C141 are  
high-speed CMOS 1K by 8 dual-port static RAMs. Two ports  
are provided permitting independent access to any location in  
memory. The CY7C130/ CY7C131 can be utilized as either a  
standalone 8-bit dual-port static RAM or as a master dual-port  
RAM in conjunction with the CY7C140/CY7C141 slave du-  
al-port device in systems requiring 16-bit or greater word  
widths. It is the solution to applications requiring shared or  
buffered data, such as cache memory for DSP, bit-slice, or  
multiprocessor designs.  
• Low operating power: I = 90 mA (max.)  
CC  
• Fully asynchronous operation  
• Automatic power-down  
• Master CY7C130/CY7C131 easily expands data bus  
width to 16 or more bits using slave CY7C140/CY7C141  
• BUSY output flag on CY7C130/CY7C131; BUSY input  
on CY7C140/CY7C141  
• INT flag for port-to-port communication  
• Availablein 48-pin DIP (CY7C130/140), 52-pin PLCCand  
52-pin TQFP  
• Pin-compatible and functionally equivalent to  
IDT7130/IDT7140  
Each port has independent control pins; chip enable (CE),  
write enable (R/W), and output enable (OE). Two flags are  
provided on each port, BUSY and INT. BUSY signals that the  
port is trying to access the same location currently being ac-  
cessed by the other port. INT is an interrupt flag indicating that  
data has been placed in a unique location (3FF for the left port  
and 3FE for the right port). An automatic power-down feature  
is controlled independently on each port by the chip enable  
(CE) pins.  
The CY7C130 and CY7C140 are available in 48-pin DIP. The  
CY7C131 and CY7C141 are available in 52-pin PLCC and  
PQFP.  
Logic Block Diagram  
Pin Configurations  
R/W  
L
R/W  
R
CE  
L
CE  
R
DIP  
Top View  
OE  
L
OE  
R
V
48  
CE  
R/W  
BUSY  
CC  
1
L
L
47  
46  
45  
44  
CE  
R
R/W  
BUSY  
INT  
2
3
4
5
6
L
R
I/O  
I/O  
I/O  
7L  
7R  
0R  
I/O  
CONTROL  
I/O  
CONTROL  
INT  
R
L
OE  
R
L
I/O  
0L  
A
0L  
OE  
A
0R  
43  
42  
R
[1]  
A
A
A
BUSY  
BUSY  
1L  
2L  
L
R
7
8
9
10  
11  
12  
A
A
A
A
41  
40  
1R  
A
A
A
2R  
3L  
4L  
5L  
9L  
0L  
9R  
0R  
MEMORY  
ARRAY  
ADDRESS  
DECODER  
ADDRESS  
DECODER  
A
A
39  
38  
37  
36  
35  
34  
3R  
4R  
A
A
A
6L  
5R  
7C130  
A
A
A
8R  
A
A
13 7C140  
6R  
7L  
8L  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
7R  
A
9L  
I/O  
A
9R  
33  
32  
31  
30  
29  
28  
27  
26  
25  
0L  
1L  
2L  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
ARBITRATION  
LOGIC  
7R  
6R  
(7C130/7C131 ONLY)  
AND  
3L  
4L  
5R  
CE  
L
CE  
R
4R  
INTERRUPT LOGIC  
OE  
L
OE  
R
3R  
5L  
6L  
7L  
2R  
R/W  
R/W  
R
L
I/O  
I/O  
1R  
GND  
[2]  
L
0R  
[2]  
INT  
INT  
R
C130-2  
C130-1  
Notes:  
1. CY7C130/CY7C131 (Master): BUSY is open drain output and requires pull-up resistor  
CY7C140/CY7C141 (Slave): BUSY is input.  
2. Open drain outputs: pull-up resistor required  
s
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
May 1989 – Revised March 27, 1997  
1234567...16

中文翻译

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