Datasheet > CY7C1304CV25

CY7C1304CV25

更新时间： 2024-11-01 05:09:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
18页	301K
描述
9-Mbit Burst of 4 Pipelined SRAM with QDR⑩ Architecture

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中文翻译

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数据手册

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CY7C1304CV25 数据手册

CY7C1304CV25

PRELIMINARY

9-MbitBurstof4Pipelined SRAMwithQDR™Architecture

Features

Functional Description

• Separate independent Read and Write data ports

— Supports concurrent transactions

• 167-MHz Clock for high bandwidth

— 2.5 ns Clock-to-Valid access time

• 4-Word Burst for reducing the address bus frequency

The CY7C1304CV25 is a 2.5V Synchronous Pipelined SRAM

equipped with QDR™ architecture. QDR architecture consists

of two separate ports to access the memory array. The Read

port has dedicated Data Outputs to support Read operations

and the Write port has dedicated Data Inputs to support Write

operations. QDR architecture has separate data inputs and

data outputs to completely eliminate the need to “turn-around”

the data bus required with common I/O devices. Access to

each port is accomplished through a common address bus.

Addresses for Read and Write addresses are latched on

alternate rising edges of the input (K) clock. Accesses to the

device’s Read and Write ports are completely independent of

one another. In order to maximize data throughput, both Read

and Write ports are equipped with Double Data Rate (DDR)

interfaces. Each address location is associated with four 18-bit

words. Since data can be transferred into and out of the device

on every rising edge of both input clock (K/K and C/C) memory

bandwidth is maximized while simplifying system design by

eliminating bus “turn-arounds.”

• Double Data Rate (DDR) interfaces on both Read and

Write Ports (data transferred at 333 MHz) @167 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) account for clock skew

and flight time mismatching

• Single multiplexed address input bus latches address

inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

Depth expansion is accomplished with Port Selects for each

• 2.5V core power supply with HSTL Inputs and Outputs

port. Port selects allow each port to operate independently.

• 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165-ball

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

(11x15 matrix)

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–1.9V)

• JTAG 1149.1 compatible test access port

Configurations

CY7C1304CV25 – 512K x 18

Logic Block Diagram (CY7C1304CV25)

D_[17:0]

Write Write Write Write

Reg Reg Reg

Reg

•

Address

A_(16:0)

Address

A_(16:0)

CLK

Gen.

RPS

Control

Logic

Read Data Reg.

Vref

WPS

BWS_[0:1]

Reg.

Control

Logic

Q_[17:0]

Cypress Semiconductor Corporation

•

3901 North First Street

San Jose, CA 95134

•

408-943-2600

Document #: 38-05494 Rev. *A

Revised June 1, 2004

12 3 4 5 6 7...18

中文翻译

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与CY7C1304CV25相关器件

型号	品牌	获取价格	描述	数据表
CY7C1304CV25-100BZC	CYPRESS	获取价格	9-Mbit Burst of 4 Pipelined SRAM with QDR⑩ Ar
CY7C1304CV25-133BZC	CYPRESS	获取价格	9-Mbit Burst of 4 Pipelined SRAM with QDR⑩ Ar
CY7C1304CV25-167BZC	CYPRESS	获取价格	9-Mbit Burst of 4 Pipelined SRAM with QDR⑩ Ar
CY7C1304DV25	CYPRESS	获取价格	RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
CY7C1304DV25_06	CYPRESS	获取价格	9-Mbit Burst of 4 Pipelined SRAM with QDR⑩ Ar
CY7C1304DV25-100BZC	CYPRESS	获取价格	QDR SRAM, 512KX18, 3ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165
CY7C1304DV25-133BZC	CYPRESS	获取价格	QDR SRAM, 512KX18, 3ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165
CY7C1304DV25-167BZC	CYPRESS	获取价格	9-Mbit Burst of 4 Pipelined SRAM with QDR⑩ Ar
CY7C1304DV25-167BZI	CYPRESS	获取价格	9-Mbit Burst of 4 Pipelined SRAM with QDR⑩ Ar
CY7C1304DV25-167BZXC	CYPRESS	获取价格	9-Mbit Burst of 4 Pipelined SRAM with QDR⑩ Ar

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