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CY7C1046B-15VC PDF预览

CY7C1046B-15VC

更新时间: 2024-09-13 03:00:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
8页 138K
描述
1M x 4 Static RAM

CY7C1046B-15VC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOJ包装说明:0.400 INCH, PLASTIC, SOJ-32
针数:32Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.76Is Samacsys:N
最长访问时间:15 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-J32JESD-609代码:e0
长度:20.955 mm内存密度:4194304 bit
内存集成电路类型:STANDARD SRAM内存宽度:4
湿度敏感等级:2功能数量:1
端子数量:32字数:1048576 words
字数代码:1000000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:1MX4输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装等效代码:SOJ32,.44封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:5 V
认证状态:Not Qualified座面最大高度:3.7592 mm
最大待机电流:0.0002 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.15 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:10.16 mm
Base Number Matches:1

CY7C1046B-15VC 数据手册

 浏览型号CY7C1046B-15VC的Datasheet PDF文件第2页浏览型号CY7C1046B-15VC的Datasheet PDF文件第3页浏览型号CY7C1046B-15VC的Datasheet PDF文件第4页浏览型号CY7C1046B-15VC的Datasheet PDF文件第5页浏览型号CY7C1046B-15VC的Datasheet PDF文件第6页浏览型号CY7C1046B-15VC的Datasheet PDF文件第7页 
046B  
CY7C1046B  
1M x 4 Static RAM  
sion is provided by an active LOW Chip Enable (CE), an active  
LOW Output Enable (OE), and three-state drivers. Writing to  
the device is accomplished by taking Chip Enable (CE) and  
Write Enable (WE) inputs LOW. Data on the four I/O pins (I/O0  
through I/O3) is then written into the location specified on the  
address pins (A0 through A19).  
Features  
• High speed  
— tAA = 12 ns  
• Low active power  
— 935 mW (max.)  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins will appear  
on the I/O pins.  
• Low CMOS standby power (L version)  
— 2.75 mW (max.)  
2.0V Data Retention (400 µW at 2.0V retention)  
Automatic power-down when deselected  
TTL-compatible inputs and outputs  
Easy memory expansion with CE and OE features  
The four input/output pins (I/O0 through I/O3) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW, and WE LOW).  
Functional Description  
The CY7C1046B is available in a standard 400-mil-wide  
32-pin SOJ package with center power and ground (revolu-  
tionary) pinout.  
The CY7C1046B is a high-performance CMOS static RAM or-  
ganized as 1,048,576 words by 4 bits. Easy memory expan-  
Logic Block Diagram  
Pin Configuration  
SOJ  
Top View  
A0  
A1  
32  
31  
30  
29  
28  
1
2
3
4
5
A19  
A18  
A17  
A16  
A15  
A2  
A3  
A4  
CE  
I/O0  
VCC  
27  
26  
25  
6
7
8
9
10  
11  
OE  
I/O3  
GND  
VCC  
I/O2  
A14  
A13  
A12  
A11  
A10  
NC  
INPUT BUFFER  
A
0
24  
23  
GND  
I/O1  
WE  
A
1
A
2
22  
21  
20  
19  
18  
17  
I/O  
0
A
A5  
A6  
A7  
A8  
A9  
3
4
12  
13  
14  
15  
16  
A
A
I/O  
I/O  
I/O  
5
6
1
2
3
1M x 4  
A
ARRAY  
A
7
A
8
A
9
A
10  
1046B2  
POWER  
DOWN  
COLUMN  
DECODER  
CE  
WE  
1046B1  
OE  
Selection Guide  
7C1046B-12  
7C1046B-15  
7C1046B-20  
Maximum Access Time (ns)  
12  
170  
8
15  
150  
8
20  
130  
8
Maximum Operating Current (mA)  
Maximum CMOS Standby  
Current (mA)  
Coml  
L version  
0.5  
0.5  
0.5  
Shaded areas contain advance information.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-05144 Rev. **  
Revised September 6, 2001  

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