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CY7C1046BN-15VCT PDF预览

CY7C1046BN-15VCT

更新时间: 2024-09-13 21:19:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
9页 275K
描述
Standard SRAM, 1MX4, 15ns, CMOS, PDSO32, 0.400 INCH, SOJ-32

CY7C1046BN-15VCT 技术参数

生命周期:Obsolete零件包装代码:SOJ
包装说明:SOJ,针数:32
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.62
最长访问时间:15 nsJESD-30 代码:R-PDSO-J32
长度:20.955 mm内存密度:4194304 bit
内存集成电路类型:STANDARD SRAM内存宽度:4
功能数量:1端子数量:32
字数:1048576 words字数代码:1000000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:1MX4
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL认证状态:Not Qualified
座面最大高度:3.7592 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
宽度:10.16 mmBase Number Matches:1

CY7C1046BN-15VCT 数据手册

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CY7C1046BN  
1M x 4 Static RAM  
You write to the device by taking Chip Enable (CE) and Write  
Enable (WE) inputs LOW. Data on the four IO pins (IO0  
Features  
• Low active power  
through IO3) is then written into the location specified on the  
address pins (A0 through A19).  
— 825 mW (max)  
• Low CMOS standby power  
You read from the device by taking Chip Enable (CE) and  
Output Enable (OE) LOW while forcing Write Enable (WE)  
HIGH. Under these conditions, the contents of the memory  
location specified by the address pins appears on the IO pins.  
— 44 mW (max)  
• 2.0V data retention (400 μW at 2.0V retention)  
• Automatic power down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE and OE features  
• Available in non Pb-free 400 mil wide 32-pin SOJ package  
The four input and output pins (IO0 through IO3) are placed in  
a high impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or when the write  
operation is active (CE LOW, and WE LOW).  
Functional Description  
The CY7C1046BN is available in a standard 400-mil-wide  
32-pin SOJ package with center power and ground (revolu-  
tionary) pinout.  
The CY7C1046BN is a high performance CMOS static RAM  
organized as 1,048,576 words by 4 bits. Easy memory  
expansion is provided by an active LOW Chip Enable (CE), an  
active LOW Output Enable (OE), and tri-state drivers.  
Logic Block Diagram  
Pin Configuration  
SOJ  
TOP VIEW  
A
A
32  
31  
30  
29  
1
2
3
4
5
6
A
0
1
19  
A
A
A
A
18  
17  
16  
15  
A
2
A
A
3
4
INPUT BUFFER  
A
1
0
28  
27  
A
CE  
OE  
A
2
IO  
26  
25  
IO  
GND  
7
8
IO  
0
3
0
A
3
V
CC  
A
4
24  
23  
GND  
IO  
1
WE  
9
10  
11  
V
A
CC  
IO  
IO  
IO  
5
1
2
3
1M x 4  
IO  
A
2
6
ARRAY  
22  
21  
20  
A
A
7
14  
A
A
8
A
5
12  
13  
14  
15  
16  
13  
A
9
A
A
12  
6
A
10  
19  
18  
17  
A
7
A
11  
A
A
8
10  
A
9
NC  
POWER  
DOWN  
COLUMN  
DECODER  
CE  
WE  
1046B–1  
1046B–2  
OE  
Selection Guide  
7C1046BN-15  
Maximum Access Time (ns)  
15  
150  
8
Maximum Operating Current (mA)  
Maximum CMOS Standby Current (mA)  
Cypress Semiconductor Corporation  
Document #: 001-11924 Rev. **  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised November 30, 2006  

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