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CY7C1046CV33 PDF预览

CY7C1046CV33

更新时间: 2024-09-12 22:34:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
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描述
1M x 4 Static RAM

CY7C1046CV33 数据手册

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CY7C1046CV33  
1M x 4 Static RAM  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. Data on the four I/O  
pins (I/O0 through I/O3) is then written into the location  
specified on the address pins (A0 through A19).  
Features  
• High speed  
— tAA = 10ns  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins will appear  
on the I/O pins.  
• Low active power for 10 ns speed  
— 324 mW (max.)  
• 2.0V data retention  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE and OE features  
The four input/output pins (I/O0 through I/O3) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a Write  
operation (CE LOW, and WE LOW).  
Functional Description[1]  
The CY7C1046CV33 is available in a standard 400-mil-wide  
32-pin SOJ package with center power and ground (revolu-  
tionary) pinout.  
The CY7C1046CV33 is a high-performance CMOS static  
RAM organized as 1,048,576 words by 4 bits. Easy memory  
expansion is provided by an active LOW Chip Enable (CE), an  
active LOW Output Enable (OE), and three-state drivers.  
Logic Block Diagram  
Pin Configuration  
SOJ  
Top View  
A
A
32  
31  
30  
29  
1
2
3
4
5
6
A
0
1
19  
A
A
A
A
18  
17  
16  
15  
A
2
A
A
3
4
28  
27  
26  
25  
INPUT BUFFER  
A
1
0
A
CE  
OE  
I/O  
GND  
I/O  
7
8
0
A
3
2
I/O  
0
V
A
CC  
3
4
A
24  
23  
GND  
9
10  
11  
V
I/O  
CC  
A
6
I/O  
I/O  
I/O  
5
1
2
3
1M x 4  
I/O  
A
2
1
ARRAY  
A
WE  
22  
21  
20  
19  
18  
17  
A
A
A
7
14  
13  
12  
A
8
A
A
12  
13  
14  
15  
16  
5
9
A
A
10  
6
A
A
A
7
11  
10  
A
8
POWER  
DOWN  
COLUMN  
DECODER  
A
CE  
NC  
9
WE  
OE  
Selection Guide  
-8[2]  
8
-10  
10  
90  
10  
-12  
-15  
Unit  
ns  
Maximum Access Time  
12  
85  
10  
15  
80  
10  
Maximum Operating Current  
100  
10  
mA  
mA  
Maximum CMOS Standby Current  
Notes:  
1. For guidelines on SRAM system design, please refer to the System Design GuidelinesCypress application note, available on the internet at www.cypress.com.  
2. Shaded areas contain advance information.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-05003 Rev. *A  
Revised September 13, 2002  

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