5秒后页面跳转
CY7C1046D-10VXIT PDF预览

CY7C1046D-10VXIT

更新时间: 2024-09-15 13:07:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
15页 446K
描述
暂无描述

CY7C1046D-10VXIT 数据手册

 浏览型号CY7C1046D-10VXIT的Datasheet PDF文件第2页浏览型号CY7C1046D-10VXIT的Datasheet PDF文件第3页浏览型号CY7C1046D-10VXIT的Datasheet PDF文件第4页浏览型号CY7C1046D-10VXIT的Datasheet PDF文件第5页浏览型号CY7C1046D-10VXIT的Datasheet PDF文件第6页浏览型号CY7C1046D-10VXIT的Datasheet PDF文件第7页 
CY7C1046D  
4-Mbit (1 M × 4) Static RAM  
4-Mbit (1  
M × 4) Static RAM  
Features  
Functional Description  
Pin- and function-compatible with CY7C1046B  
The CY7C1046D[1] is a high-performance CMOS static RAM  
organized as 1M words by 4 bits. Easy memory expansion is  
provided by an active LOW Chip Enable (CE), an active LOW  
Output Enable (OE), and tri-state drivers. Writing to the device  
is accomplished by taking Chip Enable (CE) and Write Enable  
(WE) inputs LOW. Data on the four I/O pins (I/O0 through I/O3)  
is then written into the location specified on the address pins  
(A0 through A19).  
High speed  
tAA = 10 ns  
CMOS for optimum speed/power  
Low active power  
ICC = 90 mA @ 10 ns  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins will appear  
on the I/O pins.  
Low CMOS Standby Power  
ISB2 = 10 mA  
Data Retention at 2.0 V  
Automatic power-down when deselected  
TTL-compatible inputs and outputs  
The four input/output pins (I/O0 through I/O3) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW, and WE LOW).  
Easy memory expansion with CE and OE features  
Available in lead-free 400-mil-wide 32-pin SOJ package  
The CY7C1046D is available in a standard 400-mil-wide  
32-pin SOJ package with center power and ground  
(revolutionary) pinout.  
Logic Block Diagram  
INPUT BUFFER  
A
1
0
A
A
2
I/O  
0
A
3
A
4
A
6
I/O  
I/O  
I/O  
5
1
2
3
1M x 4  
A
A
7
A
8
A
9
A
10  
POWER  
DOWN  
COLUMN  
DECODER  
CE  
WE  
OE  
Note  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
Document Number: 38-05705 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised December 1, 2010  
[+] Feedback  

与CY7C1046D-10VXIT相关器件

型号 品牌 获取价格 描述 数据表
CY7C1046DV33 CYPRESS

获取价格

4-Mbit (1M x 4) Static RAM
CY7C1046DV33_10 CYPRESS

获取价格

4-Mbit (1 M × 4) Static RAM
CY7C1046DV33-10VXI CYPRESS

获取价格

4-Mbit (1M x 4) Static RAM
CY7C1046DV33-10VXIT CYPRESS

获取价格

暂无描述
CY7C1049 CYPRESS

获取价格

512K x 8 Static RAM
CY7C1049-15VC CYPRESS

获取价格

512K x 8 Static RAM
CY7C1049-15VCT CYPRESS

获取价格

暂无描述
CY7C1049-17VC CYPRESS

获取价格

512K x 8 Static RAM
CY7C1049-20VC CYPRESS

获取价格

512K x 8 Static RAM
CY7C1049-20VCT CYPRESS

获取价格

Standard SRAM, 512KX8, 20ns, CMOS, PDSO36, 0.400 INCH, PLASTIC, SOJ-36