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CY7C1049B-15VC PDF预览

CY7C1049B-15VC

更新时间: 2024-02-13 06:32:38
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
10页 135K
描述
512K x 8 Static RAM

CY7C1049B-15VC 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOJ包装说明:SOJ,
针数:36Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.65最长访问时间:15 ns
JESD-30 代码:R-PDSO-J36JESD-609代码:e4
长度:23.495 mm内存密度:4194304 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:36字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:512KX8封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:3.683 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:NICKEL PALLADIUM GOLD
端子形式:J BEND端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:10.16 mmBase Number Matches:1

CY7C1049B-15VC 数据手册

 浏览型号CY7C1049B-15VC的Datasheet PDF文件第2页浏览型号CY7C1049B-15VC的Datasheet PDF文件第3页浏览型号CY7C1049B-15VC的Datasheet PDF文件第4页浏览型号CY7C1049B-15VC的Datasheet PDF文件第5页浏览型号CY7C1049B-15VC的Datasheet PDF文件第6页浏览型号CY7C1049B-15VC的Datasheet PDF文件第7页 
049B  
CY7C1049B  
512K x 8 Static RAM  
is provided by an active LOW Chip Enable (CE), an active  
LOW Output Enable (OE), and three-state drivers. Writing to  
the device is accomplished by taking Chip Enable (CE) and  
Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0  
through I/O7) is then written into the location specified on the  
address pins (A0 through A18).  
Features  
• High speed  
— tAA = 12 ns  
• Low active power  
— 1320 mW (max.)  
Reading from the device is accomplished by taking Chip En-  
able (CE) and Output Enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins will appear  
on the I/O pins.  
• Low CMOS standby power (Commercial L version)  
— 2.75 mW (max.)  
• 2.0V Data Retention (400 µW at 2.0V retention)  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE and OE features  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW, and WE LOW).  
Functional Description[1]  
The CY7C1049B is available in a standard 400-mil-wide  
36-pin SOJ package with center power and ground (revolu-  
tionary) pinout.  
The CY7C1049B is a high-performance CMOS static RAM or-  
ganized as 524,288 words by 8 bits. Easy memory expansion  
Logic Block Diagram  
Pin Configuration  
SOJ  
Top View  
A
A
36  
35  
34  
33  
32  
1
2
3
4
5
6
7
8
9
NC  
0
1
A
A
A
A
18  
17  
16  
15  
A
2
A
A
3
4
CE  
I/O  
31  
30  
29  
28  
OE  
I/O  
0
1
7
I/O  
I/O  
V
I/O  
6
0
GND  
INPUT BUFFER  
CC  
27  
26  
25  
GND 10  
V
CC  
A
1
0
I/O  
I/O  
I/O  
I/O3  
WE  
I/O  
I/O  
A
11  
12  
13  
1
5
4
2
A
A
2
24  
23  
22  
21  
20  
19  
14  
2
A
A
A
A
A
A
5
3
4
14  
15  
16  
17  
18  
13  
A
A
12  
6
A
7
A
11  
10  
5
6
I/O  
I/O  
I/O  
3
4
5
512K x 8  
ARRAY  
A
A
8
A
9
NC  
A
7
A
8
A
9
A
10  
I/O  
6
7
POWER  
DOWN  
COLUMN  
DECODER  
CE  
I/O  
WE  
OE  
Selection Guide  
7C1049B-12 7C1049B-15 7C1049B-17 7C1049B-20 7C1049B-25  
Maximum Access Time (ns)  
12  
15  
17  
195  
8
20  
185  
8
25  
180  
8
Maximum Operating Current (mA)  
240  
220  
Maximum CMOS Standby  
Current (mA)  
Coml  
8
-
8
-
Coml/Indl L  
Indl  
0.5  
-
0.5  
9
0.5  
9
-
-
Note:  
1. For guidelines on SRAM system design, please refer to the System Design GuidelinesCypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-05169 Rev. *A  
Revised September 13, 2002  

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