CY7C1046BN
1M x 4 Static RAM
You write to the device by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. Data on the four IO pins (IO0
Features
• Low active power
through IO3) is then written into the location specified on the
address pins (A0 through A19).
— 825 mW (max)
• Low CMOS standby power
You read from the device by taking Chip Enable (CE) and
Output Enable (OE) LOW while forcing Write Enable (WE)
HIGH. Under these conditions, the contents of the memory
location specified by the address pins appears on the IO pins.
— 44 mW (max)
• 2.0V data retention (400 μW at 2.0V retention)
• Automatic power down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in non Pb-free 400 mil wide 32-pin SOJ package
The four input and output pins (IO0 through IO3) are placed in
a high impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or when the write
operation is active (CE LOW, and WE LOW).
Functional Description
The CY7C1046BN is available in a standard 400-mil-wide
32-pin SOJ package with center power and ground (revolu-
tionary) pinout.
The CY7C1046BN is a high performance CMOS static RAM
organized as 1,048,576 words by 4 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers.
Logic Block Diagram
Pin Configuration
SOJ
TOP VIEW
A
A
32
31
30
29
1
2
3
4
5
6
A
0
1
19
A
A
A
A
18
17
16
15
A
2
A
A
3
4
INPUT BUFFER
A
1
0
28
27
A
CE
OE
A
2
IO
26
25
IO
GND
7
8
IO
0
3
0
A
3
V
CC
A
4
24
23
GND
IO
1
WE
9
10
11
V
A
CC
IO
IO
IO
5
1
2
3
1M x 4
IO
A
2
6
ARRAY
22
21
20
A
A
7
14
A
A
8
A
5
12
13
14
15
16
13
A
9
A
A
12
6
A
10
19
18
17
A
7
A
11
A
A
8
10
A
9
NC
POWER
DOWN
COLUMN
DECODER
CE
WE
1046B–1
1046B–2
OE
Selection Guide
7C1046BN-15
Maximum Access Time (ns)
15
150
8
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Cypress Semiconductor Corporation
Document #: 001-11924 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 30, 2006
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