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CY7C1046B

更新时间： 2024-09-13 05:19:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
8页 138K
描述
1M x 4 Static RAM

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CY7C1046B 数据手册

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046B  
CY7C1046B  
1M x 4 Static RAM  
sion is provided by an active LOW Chip Enable (CE), an active  
LOW Output Enable (OE), and three-state drivers. Writing to  
the device is accomplished by taking Chip Enable (CE) and  
Write Enable (WE) inputs LOW. Data on the four I/O pins (I/O0  
through I/O3) is then written into the location specified on the  
address pins (A0 through A19).  
Features  
• High speed  
— tAA = 12 ns  
• Low active power  
— 935 mW (max.)  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins will appear  
on the I/O pins.  
• Low CMOS standby power (L version)  
— 2.75 mW (max.)  
• 2.0V Data Retention (400 µW at 2.0V retention)  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE and OE features  
The four input/output pins (I/O0 through I/O3) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW, and WE LOW).  
Functional Description  
The CY7C1046B is available in a standard 400-mil-wide  
32-pin SOJ package with center power and ground (revolu-  
tionary) pinout.  
The CY7C1046B is a high-performance CMOS static RAM or-  
ganized as 1,048,576 words by 4 bits. Easy memory expan-  
Logic Block Diagram  
Pin Configuration  
SOJ  
Top View  
A0  
A1  
32  
31  
30  
29  
28  
1
2
3
4
5
A19  
A18  
A17  
A16  
A15  
A2  
A3  
A4  
CE  
I/O0  
VCC  
27  
26  
25  
6
7
8
9
10  
11  
OE  
I/O3  
GND  
VCC  
I/O2  
A14  
A13  
A12  
A11  
A10  
NC  
INPUT BUFFER  
A
0
24  
23  
GND  
I/O1  
WE  
A
1
A
2
22  
21  
20  
19  
18  
17  
I/O  
0
A
A5  
A6  
A7  
A8  
A9  
3
4
12  
13  
14  
15  
16  
A
A
I/O  
I/O  
I/O  
5
6
1
2
3
1M x 4  
A
ARRAY  
A
7
A
8
A
9
A
10  
1046B–2  
POWER  
DOWN  
COLUMN  
DECODER  
CE  
WE  
1046B–1  
OE  
Selection Guide  
7C1046B-12  
7C1046B-15  
7C1046B-20  
Maximum Access Time (ns)  
12  
170  
8
15  
150  
8
20  
130  
8
Maximum Operating Current (mA)  
Maximum CMOS Standby  
Current (mA)  
Com’l  
L version  
0.5  
0.5  
0.5  
Shaded areas contain advance information.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05144 Rev. **  
Revised September 6, 2001  
12345678

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