Datasheet > CY7C1012AV25

CY7C1012AV25

更新时间： 2024-11-09 05:09:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
9页	315K
描述
512K x 24 Static RAM

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中文翻译

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数据手册

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CY7C1012AV25 数据手册

CY7C1012AV25

PRELIMINARY

512K x 24 Static RAM

Writing the data bytes into the SRAM is accomplished when

the chip select controlling that byte is LOW and the write

enable input (WE) input is LOW. Data on the respective

input/output (I/O) pins is then written into the location specified

on the address pins (A₀–A₁₆). Asserting all of the chip selects

LOW and write enable LOW will write all 24 bits of data into

the SRAM. Output enable (OE) is ignored while in WRITE

mode.

Features

• High speed

— t_AA= 8, 10, 12 ns

• Low active power

— 1080 mW (max.)

• Operating voltages of 2.5 ± 0.2V

• 1.5V data retention

• Automatic power-down when deselected

• TTL-compatible inputs and outputs

• Easy memory expansion with CE₀, CE₁and CE₂

features

Data bytes can also be individually read from the device.

Reading a byte is accomplished when the chip select

controlling that byte is LOW and write enable (WE) HIGH while

output enable (OE) remains LOW. Under these conditions, the

contents of the memory location specified on the address pins

will appear on the specified data input/output (I/O) pins.

Asserting all the chip selects LOW will read all 24 bits of data

from the SRAM.

Functional Description

The CY7C1012AV25 is a high-performance CMOS static

RAM organized as 512K words by 24 bits. Each data byte is

separately controlled by the individual chip selects (CE₀, CE₁,

CE₂). CE₀controls the data on the I/O₀–I/O₇, while CE₁

controls the data on I/O₈–I/O₁₅, and CE₂controls the data on

the data pins I/O₁₆–I/O₂₃. This device has an automatic

power-down feature that significantly reduces power

consumption when deselected.

The 24 I/O pins (I/O₀–I/O₂₃) are placed in a high-impedance

state when all the chip selects are HIGH or when the output

enable (OE) is HIGH during a READ mode. For further details,

refer to the truth table of this data sheet.

The CY7C1012AV25 is available in a standard 119-ball BGA.

Functional Block Diagram

INPUT BUFFER

I/O –I/O

512K x 24

ARRAY

I/O –I/O

4096 x 4096

I/O –I/O

CE , CE , CE

COLUMN

DECODER

CONTROL LOGIC

Selection Guide

-8

-10

-12

Unit

Maximum Access Time

Maximum Operating Current

Commercial

300

275

260

Industrial

Maximum CMOS Standby Current

Commercial/Industrial

Cypress Semiconductor Corporation

Document #: 38-05337 Rev. **

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised January 27, 2003

12 3 4 5 6 7...9

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与CY7C1012AV25相关器件

型号	品牌	获取价格	描述	数据表
CY7C1012AV25-10BGC	CYPRESS	获取价格	512K x 24 Static RAM
CY7C1012AV25-10BGI	CYPRESS	获取价格	512K x 24 Static RAM
CY7C1012AV25-12BGC	CYPRESS	获取价格	512K x 24 Static RAM
CY7C1012AV25-12BGI	CYPRESS	获取价格	512K x 24 Static RAM
CY7C1012AV25-8BGC	CYPRESS	获取价格	512K x 24 Static RAM
CY7C1012AV25-8BGI	CYPRESS	获取价格	512K x 24 Static RAM
CY7C1012AV33	CYPRESS	获取价格	512K x 24 Static RAM
CY7C1012AV33_06	CYPRESS	获取价格	512K x 24 Static RAM
CY7C1012AV33_11	CYPRESS	获取价格	512 K × 24 Static RAM TTL-compatible inputs a
CY7C1012AV33-10BGC	CYPRESS	获取价格	512K x 24 Static RAM

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